image/svg+xml MOVDQ2Q—Move Quadword from XMM to MMX Technology Register Instruction Operand Encoding Description Moves the low quadword from the source operand (second operand) to the destination operand (first operand). The source operand is an XMM register and the destination operand is an MMX technology register. This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the MOVDQ2Q instruction is executed. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST := SRC[63:0]; Intel C/C ++ Compiler Intrinsic Equivalent MOVDQ2Q:__m64 _mm_movepi64_pi64 ( __m128i a) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #NMIf CR0.TS[bit 3] = 1. #UDIf CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #MFIf there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in protected mode. Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. OpcodeInstructionOp/ En 64-Bit Mode Compat/ Leg Mode Description F2 0F D6 /rMOVDQ2Q mm , xmm RMValidValidMove low quadword from xmm to mmx register. Op/EnOperand 1Operand 2Operand 3Operand 4 RMModRM:reg (w)ModRM:r/m (r)NANA This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .