image/svg+xml LZCNT— Count the Number of Leading Zero Bits Instruction Operand Encoding Description Counts the number of leading most significant zero bits in a source operand (second operand) returning the result into a destination (first operand). LZCNT differs from BSR. For example, LZCNT will produce the operand size when the input operand is zero. It should be noted that on processors that do not support LZCNT, the instruction byte encoding is executed as BSR. In 64-bit mode 64-bit operand size requires REX.W=1. Operation temp := OperandSize - 1 DEST := 0 WHILE (temp >= 0) AND (Bit(SRC, temp) = 0) DO temp := temp - 1 DEST := DEST+ 1 OD IF DEST = OperandSize CF := 1 ELSE CF := 0 FI IF DEST = 0 ZF := 1 ELSE ZF := 0 FI Flags Affected ZF flag is set to 1 in case of zero output (most significant bit of the source is set), and to 0 otherwise, CF flag is set to 1 if input was zero and cleared otherwise. OF, SF, PF and AF flags are undefined. Intel C/C++ Compiler Intrinsic Equivalent LZCNT:unsigned __int32 _lzcnt_u32(unsigned __int32 src); LZCNT:unsigned __int64 _lzcnt_u64(unsigned __int64 src); Opcode/InstructionOp/ En 64/32 -bit Mode CPUID Feature Flag Description F3 0F BD /r LZCNT r16, r/m16 RMV/VLZCNTCount the number of leading zero bits in r/m16, return result in r16. F3 0F BD /r LZCNT r32, r/m32 RMV/VLZCNTCount the number of leading zero bits in r/m32, return result in r32. F3 REX.W 0F BD /r LZCNT r64, r/m64 RMV/N.E.LZCNTCount the number of leading zero bits in r/m64, return result in r64. Op/EnOperand 1Operand 2Operand 3Operand 4 RMModRM:reg (w)ModRM:r/m (r)NANA image/svg+xml Protected Mode Exceptions #GP(0)For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector. #SS(0)For an illegal address in the SS segment. #PF (fault-code)For a page fault. #AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UDIf LOCK prefix is used. Real-Address Mode Exceptions #GP(0)If any part of the operand lies outside of the effective address space from 0 to 0FFFFH. #SS(0)For an illegal address in the SS segment. #UDIf LOCK prefix is used. Virtual 8086 Mode Exceptions #GP(0)If any part of the operand lies outside of the effective address space from 0 to 0FFFFH. #SS(0)For an illegal address in the SS segment. #PF (fault-code)For a page fault. #AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UDIf LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #GP(0)If the memory address is in a non-canonical form. #SS(0)If a memory address referencing the SS segment is in a non-canonical form. #PF (fault-code)For a page fault. #AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UDIf LOCK prefix is used. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .