LTR—Load Task RegisterInstruction Operand EncodingDescriptionLoads the source operand into the segment selector field of the task register. The source operand (a general-purpose register or a memory location) contains a segment selector that points to a task state segment (TSS). After the segment selector is loaded in the task register, the processor uses the segment selector to locate the segment descriptor for the TSS in the global descriptor table (GDT). It then loads the segment limit and base address for the TSS from the segment descriptor into the task register. The task pointed to by the task register is marked busy, but a switch to the task does not occur.The LTR instruction is provided for use in operating-system software; it should not be used in application programs. It can only be executed in protected mode when the CPL is 0. It is commonly used in initialization code to establish the first task to be executed.The operand-size attribute has no effect on this instruction. In 64-bit mode, the operand size is still fixed at 16 bits. The instruction references a 16-byte descriptor to load the 64-bit base.OperationIF SRC is a NULL selectorTHEN #GP(0);IF SRC(Offset) > descriptor table limit OR IF SRC(type) ≠globalTHEN #GP(segment selector); FI;Read segment descriptor;IF segment descriptor is not for an available TSS THEN #GP(segment selector); FI;IF segment descriptor is not present THEN #NP(segment selector); FI;TSSsegmentDescriptor(busy) := 1; (* Locked read-modify-write operation on the entire descriptor when setting busy flag *)TaskRegister(SegmentSelector) := SRC;TaskRegister(SegmentDescriptor) := TSSSegmentDescriptor;Flags AffectedNoneOpcodeInstructionOp/ En64-Bit ModeCompat/Leg ModeDescription0F 00 /3LTR r/m16MValidValidLoad r/m16 into task register.Op/EnOperand 1Operand 2Operand 3Operand 4MModRM:r/m (r)NANANA
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