image/svg+xml LMSW—Load Machine Status Word Instruction Operand Encoding Description Loads the source operand into the machine status word, bits 0 through 15 of register CR0. The source operand can be a 16-bit general-purpose register or a memory location. Only the low-order 4 bits of the source operand (which contains the PE, MP, EM, and TS flags) are loaded into CR0. The PG, CD, NW, AM, WP, NE, and ET flags of CR0 are not affected. The operand-size attribute has no effect on this instruction. If the PE flag of the source operand (bit 0) is set to 1, the instruction causes the processor to switch to protected mode. While in protected mode, the LMSW instruction cannot be used to clear the PE flag and force a switch back to real-address mode. The LMSW instruction is provided for use in operating-system software; it should not be used in application programs. In protected or virtual-8086 mode, it can only be executed at CPL 0. This instruction is provided for compatibility with the Intel 286 processor; programs and procedures intended to run on IA-32 and Intel 64 processors beginning with Intel386 processors should use the MOV (control registers) instruction to load the whole CR0 register. The MOV CR0 instruction can be used to set and clear the PE flag in CR0, allowing a procedure or program to switch between protected and real-address modes. This instruction is a serializing instruction. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Note that the operand size is fixed at 16 bits. See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 25 of the Intel® 64 and IA-32 Archi- tectures Software Developer’s Manual, Volume 3C , for more information about the behavior of this instruction in VMX non-root operation. Operation CR0[0:3] := SRC[0:3]; Flags Affected None Protected Mode Exceptions #GP(0)If the current privilege level is not 0. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0)If a memory operand effective address is outside the SS segment limit. #PF(fault-code)If a page fault occurs. #UD If the LOCK prefix is used. Real-Address Mode Exceptions #GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #UD If the LOCK prefix is used. OpcodeInstructionOp/ En 64-Bit Mode Compat/ Leg Mode Description 0F 01 /6LMSW r/m 16MValidValidLoads r/m 16 in machine status word of CR0. Op/EnOperand 1Operand 2Operand 3Operand 4 MModRM:r/m (r)NANANA image/svg+xml Virtual-8086 Mode Exceptions #GP(0)The LMSW instruction is not recognized in virtual-8086 mode. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0)If a memory address referencing the SS segment is in a non-canonical form. #GP(0)If the current privilege level is not 0. If the memory address is in a non-canonical form. #PF(fault-code)If a page fault occurs. #UD If the LOCK prefix is used. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .