image/svg+xmlLAR—Load Access Rights ByteInstruction Operand EncodingDescriptionLoads the access rights from the segment descriptor specified by the second operand (source operand) into the first operand (destination operand) and sets the ZF flag in the flag register. The source operand (which can be a register or a memory location) contains the segment selector for the segment descriptor being accessed. If the source operand is a memory address, only 16 bits of data are accessed. The destination operand is a general-purpose register.The processor performs access checks as part of the loading process. Once loaded in the destination register, soft-ware can perform additional checks on the access rights information. The access rights for a segment descriptor include fields located in the second doubleword (bytes 4–7) of the segment descriptor. The following fields are loaded by the LAR instruction:•Bits 7:0 are returned as 0•Bits 11:8 return the segment type.•Bit 12 returns the S flag.•Bits 14:13 return the DPL.•Bit 15 returns the P flag.•The following fields are returned only if the operand size is greater than 16 bits:—Bits 19:16 are undefined.—Bit 20 returns the software-available bit in the descriptor.—Bit 21 returns the L flag.—Bit 22 returns the D/B flag.—Bit 23 returns the G flag.—Bits 31:24 are returned as 0.This instruction performs the following checks before it loads the access rights in the destination register: •Checks that the segment selector is not NULL.•Checks that the segment selector points to a descriptor that is within the limits of the GDT or LDT being accessed•Checks that the descriptor type is valid for this instruction. All code and data segment descriptors are valid for (can be accessed with) the LAR instruction. The valid system segment and gate descriptor types are given in Table 3-53. •If the segment is not a conforming code segment, it checks that the specified segment descriptor is visible at the CPL (that is, if the CPL and the RPL of the segment selector are less than or equal to the DPL of the segment selector).If the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no access rights are loaded in the destination operand.OpcodeInstructionOp/ En64-Bit ModeCompat/Leg ModeDescription0F 02 /rLAR r16, r16/m16RMValidValidr16 := access rights referenced by r16/m160F 02 /rLAR reg, r32/m161RMValidValidreg := access rights referenced by r32/m16NOTES:1. For all loads (regardless of source or destination sizing) only bits 16-0 are used. Other bits are ignored.Op/EnOperand 1Operand 2Operand 3Operand 4RMModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlThe LAR instruction can only be executed in protected mode and IA-32e mode.OperationIF Offset(SRC) > descriptor table limitTHEN ZF := 0; ELSESegmentDescriptor := descriptor referenced by SRC;IF SegmentDescriptor(Type) ≠ conforming code segmentand (CPL > DPL) or (RPL > DPL)or SegmentDescriptor(Type) is not valid for instructionTHENZF := 0;ELSEDEST := access rights from SegmentDescriptor as given in Description section;ZF := 1;FI;FI;Flags AffectedThe ZF flag is set to 1 if the access rights are loaded successfully; otherwise, it is cleared to 0.Table 3-53. Segment and Gate TypesTypeProtected ModeIA-32e ModeNameValidNameValid0ReservedNoReservedNo1Available 16-bit TSSYesReservedNo2LDTYesLDTYes3Busy 16-bit TSSYesReservedNo416-bit call gateYesReservedNo516-bit/32-bit task gateYesReservedNo616-bit interrupt gateNoReservedNo716-bit trap gateNoReservedNo8ReservedNoReservedNo9Available 32-bit TSSYesAvailable 64-bit TSSYesAReservedNoReservedNoBBusy 32-bit TSSYesBusy 64-bit TSSYesC32-bit call gateYes64-bit call gateYesDReservedNoReservedNoE32-bit interrupt gateNo64-bit interrupt gateNoF32-bit trap gateNo64-bit trap gateNo

image/svg+xmlProtected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and the memory operand effective address is unaligned while the current privilege level is 3. #UD If the LOCK prefix is used.Real-Address Mode Exceptions#UDThe LAR instruction is not recognized in real-address mode.Virtual-8086 Mode Exceptions#UDThe LAR instruction cannot be executed in virtual-8086 mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If the memory operand effective address referencing the SS segment is in a non-canonical form.#GP(0)If the memory operand effective address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and the memory operand effective address is unaligned while the current privilege level is 3.#UD If the LOCK prefix is used.

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