image/svg+xml KXNORW/KXNORB/KXNORQ/KXNORD—Bitwise Logical XNOR Masks Instruction Operand Encoding Description Performs a bitwise XNOR between the vector mask k2 and the vector mask k3, and writes the result into vector mask k1 (three-operand form). Operation KXNORW DEST[15:0] := NOT (SRC1[15:0] BITWISE XOR SRC2[15:0]) DEST[MAX_KL-1:16] := 0 KXNORB DEST[7:0] := NOT (SRC1[7:0] BITWISE XOR SRC2[7:0]) DEST[MAX_KL-1:8] := 0 KXNORQ DEST[63:0] := NOT (SRC1[63:0] BITWISE XOR SRC2[63:0]) DEST[MAX_KL-1:64] := 0 KXNORD DEST[31:0] := NOT (SRC1[31:0] BITWISE XOR SRC2[31:0]) DEST[MAX_KL-1:32] := 0 Intel C/C++ Compiler Intrinsic Equivalent KXNORW __mmask16 _mm512_kxnor(__mmask16 a, __mmask16 b); Flags Affected None SIMD Floating-Point Exceptions None Other Exceptions See Table2-63, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg)”. Opcode/ Instruction Op/En64/32 bit Mode Support CPUID Feature Flag Description VEX.L1.0F.W0 46 /r KXNORW k1, k2, k3 RVRV/VAVX512FBitwise XNOR 16-bit masks k2 and k3 and place result in k1. VEX.L1.66.0F.W0 46 /r KXNORB k1, k2, k3 RVRV/VAVX512DQBitwise XNOR 8-bit masks k2 and k3 and place result in k1. VEX.L1.0F.W1 46 /r KXNORQ k1, k2, k3 RVRV/VAVX512BWBitwise XNOR 64-bit masks k2 and k3 and place result in k1. VEX.L1.66.0F.W1 46 /r KXNORD k1, k2, k3 RVRV/VAVX512BWBitwise XNOR 32-bit masks k2 and k3 and place result in k1. Op/EnOperand 1Operand 2Operand 3 RVRModRM:reg (w)VEX.1vvv (r)ModRM:r/m (r, ModRM:[7:6] must be 11b) This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .