image/svg+xmlKTESTW/KTESTB/KTESTQ/KTESTD—Packed Bit Test Masks and Set FlagsInstruction Operand EncodingDescriptionPerforms a bitwise comparison of the bits of the first source operand and corresponding bits in the second source operand. If the AND operation produces all zeros, the ZF is set else the ZF is clear. If the bitwise AND operation of the inverted first source operand with the second source operand produces all zeros the CF is set else the CF is clear. Only the EFLAGS register is updated.Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.OperationKTESTW TEMP[15:0] := SRC2[15:0] AND SRC1[15:0]IF (TEMP[15:0] = = 0)THEN ZF :=1;ELSE ZF := 0;FI;TEMP[15:0] := SRC2[15:0] AND NOT SRC1[15:0]IF (TEMP[15:0] = = 0)THEN CF :=1;ELSE CF := 0;FI;AF := OF := PF := SF := 0;KTESTB TEMP[7:0] := SRC2[7:0] AND SRC1[7:0]IF (TEMP[7:0] = = 0)THEN ZF :=1;ELSE ZF := 0;FI;TEMP[7:0] := SRC2[7:0] AND NOT SRC1[7:0]IF (TEMP[7:0] = = 0)THEN CF :=1;ELSE CF := 0;FI;AF := OF := PF := SF := 0;Opcode/InstructionOp En64/32 bit Mode SupportCPUID Feature FlagDescriptionVEX.L0.0F.W0 99 /rKTESTW k1, k2RRV/VAVX512DQSet ZF and CF depending on sign bit AND and ANDN of 16 bits mask register sources.VEX.L0.66.0F.W0 99 /rKTESTB k1, k2RRV/VAVX512DQSet ZF and CF depending on sign bit AND and ANDN of 8 bits mask register sources.VEX.L0.0F.W1 99 /rKTESTQ k1, k2RRV/VAVX512BWSet ZF and CF depending on sign bit AND and ANDN of 64 bits mask register sources.VEX.L0.66.0F.W1 99 /rKTESTD k1, k2RRV/VAVX512BWSet ZF and CF depending on sign bit AND and ANDN of 32 bits mask register sources.Op/EnOperand 1Operand2RRModRM:reg (r)ModRM:r/m (r, ModRM:[7:6] must be 11b)

image/svg+xmlKTESTQ TEMP[63:0] := SRC2[63:0] AND SRC1[63:0]IF (TEMP[63:0] = = 0)THEN ZF :=1;ELSE ZF := 0;FI;TEMP[63:0] := SRC2[63:0] AND NOT SRC1[63:0]IF (TEMP[63:0] = = 0)THEN CF :=1;ELSE CF := 0;FI;AF := OF := PF := SF := 0;KTESTD TEMP[31:0] := SRC2[31:0] AND SRC1[31:0]IF (TEMP[31:0] = = 0)THEN ZF :=1;ELSE ZF := 0;FI;TEMP[31:0] := SRC2[31:0] AND NOT SRC1[31:0]IF (TEMP[31:0] = = 0)THEN CF :=1;ELSE CF := 0;FI;AF := OF := PF := SF := 0;Intel C/C++ Compiler Intrinsic EquivalentSIMD Floating-Point ExceptionsNoneOther ExceptionsSee Table2-63, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg)”.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.