image/svg+xmlKSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD—Shift Right Mask Registers Instruction Operand EncodingDescriptionShifts 8/16/32/64 bits in the second operand (source operand) right by the count specified in immediate and place the least significant 8/16/32/64 bits of the result in the destination operand. The higher bits of the destination are zero-extended. The destination is set to zero if the count value is greater than 7 (for byte shift), 15 (for word shift), 31 (for doubleword shift) or 63 (for quadword shift).OperationKSHIFTRWCOUNT := imm8[7:0]DEST[MAX_KL-1:0] := 0IF COUNT <=15THEN DEST[15:0] := SRC1[15:0] >> COUNT;FI;KSHIFTRBCOUNT := imm8[7:0]DEST[MAX_KL-1:0] := 0IF COUNT <=7THEN DEST[7:0] := SRC1[7:0] >> COUNT;FI;KSHIFTRQCOUNT := imm8[7:0]DEST[MAX_KL-1:0] := 0IF COUNT <=63THEN DEST[63:0] := SRC1[63:0] >> COUNT;FI;Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionVEX.L0.66.0F3A.W1 30 /r KSHIFTRW k1, k2, imm8RRIV/VAVX512FShift right 16 bits in k2 by immediate and write result in k1.VEX.L0.66.0F3A.W0 30 /r KSHIFTRB k1, k2, imm8RRIV/VAVX512DQShift right 8 bits in k2 by immediate and write result in k1.VEX.L0.66.0F3A.W1 31 /r KSHIFTRQ k1, k2, imm8RRIV/VAVX512BWShift right 64 bits in k2 by immediate and write result in k1.VEX.L0.66.0F3A.W0 31 /r KSHIFTRD k1, k2, imm8RRIV/VAVX512BWShift right 32 bits in k2 by immediate and write result in k1.Op/EnOperand 1Operand 2Operand 3RRIModRM:reg (w)ModRM:r/m (r, ModRM:[7:6] must be 11b)Imm8

image/svg+xmlKSHIFTRDCOUNT := imm8[7:0]DEST[MAX_KL-1:0] := 0IF COUNT <=31THEN DEST[31:0] := SRC1[31:0] >> COUNT;FI;Intel C/C++ Compiler Intrinsic EquivalentCompiler auto generates KSHIFTRW when needed.Flags AffectedNoneSIMD Floating-Point ExceptionsNoneOther ExceptionsSee Table2-63, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg)”.

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