image/svg+xmlKORTESTW/KORTESTB/KORTESTQ/KORTESTD—OR Masks And Set FlagsInstruction Operand EncodingDescriptionPerforms a bitwise OR between the vector mask register k2, and the vector mask register k1, and sets CF and ZF based on the operation result. ZF flag is set if both sources are 0x0. CF is set if, after the OR operation is done, the operation result is all 1’s.OperationKORTESTW TMP[15:0] := DEST[15:0] BITWISE OR SRC[15:0]IF(TMP[15:0]=0)THEN ZF := 1ELSE ZF := 0FI;IF(TMP[15:0]=FFFFh)THEN CF := 1ELSE CF := 0FI;KORTESTB TMP[7:0] := DEST[7:0] BITWISE OR SRC[7:0]IF(TMP[7:0]=0)THEN ZF := 1ELSE ZF := 0FI;IF(TMP[7:0]==FFh)THEN CF := 1ELSE CF := 0FI;Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionVEX.L0.0F.W0 98 /r KORTESTW k1, k2RRV/VAVX512FBitwise OR 16 bits masks k1 and k2 and update ZF and CF accordingly.VEX.L0.66.0F.W0 98 /rKORTESTB k1, k2RRV/VAVX512DQBitwise OR 8 bits masks k1 and k2 and update ZF and CF accordingly.VEX.L0.0F.W1 98 /r KORTESTQ k1, k2RRV/VAVX512BWBitwise OR 64 bits masks k1 and k2 and update ZF and CF accordingly.VEX.L0.66.0F.W1 98 /r KORTESTD k1, k2RRV/VAVX512BWBitwise OR 32 bits masks k1 and k2 and update ZF and CF accordingly.Op/EnOperand 1Operand 2RRModRM:reg (w)ModRM:r/m (r, ModRM:[7:6] must be 11b)

image/svg+xmlKORTESTQ TMP[63:0] := DEST[63:0] BITWISE OR SRC[63:0]IF(TMP[63:0]=0)THEN ZF := 1ELSE ZF := 0FI;IF(TMP[63:0]==FFFFFFFF_FFFFFFFFh)THEN CF := 1ELSE CF := 0FI;KORTESTD TMP[31:0] := DEST[31:0] BITWISE OR SRC[31:0]IF(TMP[31:0]=0)THEN ZF := 1ELSE ZF := 0FI;IF(TMP[31:0]=FFFFFFFFh)THEN CF := 1ELSE CF := 0FI;Intel C/C++ Compiler Intrinsic EquivalentKORTESTW __mmask16 _mm512_kortest[cz](__mmask16 a, __mmask16 b);Flags AffectedThe ZF flag is set if the result of OR-ing both sources is all 0s.The CF flag is set if the result of OR-ing both sources is all 1s.The OF, SF, AF, and PF flags are set to 0.Other ExceptionsSee Table2-63, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg)”.

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