image/svg+xml KORTESTW/KORTESTB/KORTESTQ/KORTESTD—OR Masks And Set Flags Instruction Operand Encoding Description Performs a bitwise OR between the vector mask register k2, and the vector mask register k1, and sets CF and ZF based on the operation result. ZF flag is set if both sources are 0x0. CF is set if, after the OR operation is done, the operation result is all 1’s. Operation KORTESTW TMP[15:0] := DEST[15:0] BITWISE OR SRC[15:0] IF(TMP[15:0]=0) THEN ZF := 1 ELSE ZF := 0 FI; IF(TMP[15:0]=FFFFh) THEN CF := 1 ELSE CF := 0 FI; KORTESTB TMP[7:0] := DEST[7:0] BITWISE OR SRC[7:0] IF(TMP[7:0]=0) THEN ZF := 1 ELSE ZF := 0 FI; IF(TMP[7:0]==FFh) THEN CF := 1 ELSE CF := 0 FI; Opcode/ Instruction Op/ En 64/32 bit Mode Support CPUID Feature Flag Description VEX.L0.0F.W0 98 /r KORTESTW k1, k2 RRV/VAVX512FBitwise OR 16 bits masks k1 and k2 and update ZF and CF accordingly. VEX.L0.66.0F.W0 98 /r KORTESTB k1, k2 RRV/VAVX512DQBitwise OR 8 bits masks k1 and k2 and update ZF and CF accordingly. VEX.L0.0F.W1 98 /r KORTESTQ k1, k2 RRV/VAVX512BWBitwise OR 64 bits masks k1 and k2 and update ZF and CF accordingly. VEX.L0.66.0F.W1 98 /r KORTESTD k1, k2 RRV/VAVX512BWBitwise OR 32 bits masks k1 and k2 and update ZF and CF accordingly. Op/EnOperand 1Operand 2 RRModRM:reg (w)ModRM:r/m (r, ModRM:[7:6] must be 11b) image/svg+xml KORTESTQ TMP[63:0] := DEST[63:0] BITWISE OR SRC[63:0] IF(TMP[63:0]=0) THEN ZF := 1 ELSE ZF := 0 FI; IF(TMP[63:0]==FFFFFFFF_FFFFFFFFh) THEN CF := 1 ELSE CF := 0 FI; KORTESTD TMP[31:0] := DEST[31:0] BITWISE OR SRC[31:0] IF(TMP[31:0]=0) THEN ZF := 1 ELSE ZF := 0 FI; IF(TMP[31:0]=FFFFFFFFh) THEN CF := 1 ELSE CF := 0 FI; Intel C/C++ Compiler Intrinsic Equivalent KORTESTW __mmask16 _mm512_kortest[cz](__mmask16 a, __mmask16 b); Flags Affected The ZF flag is set if the result of OR-ing both sources is all 0s. The CF flag is set if the result of OR-ing both sources is all 1s. The OF, SF, AF, and PF flags are set to 0. Other Exceptions See Table2-63, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg)”. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .