image/svg+xmlKMOVW/KMOVB/KMOVQ/KMOVD—Move from and to Mask Registers Instruction Operand EncodingDescriptionCopies values from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be mask registers, memory location or general purpose. The instruction cannot be used to transfer data between general purpose registers and or memory locations.When moving to a mask register, the result is zero extended to MAX_KL size (i.e., 64 bits currently). When moving to a general-purpose register (GPR), the result is zero-extended to the size of the destination. In 32-bit mode, the default GPR destination’s size is 32 bits. In 64-bit mode, the default GPR destination’s size is 64 bits. Note that VEX.W can only be used to modify the size of the GPR operand in 64b mode.Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionVEX.L0.0F.W0 90 /rKMOVW k1, k2/m16RMV/VAVX512FMove 16 bits mask from k2/m16 and store the result in k1.VEX.L0.66.0F.W0 90 /r KMOVB k1, k2/m8RMV/VAVX512DQMove 8 bits mask from k2/m8 and store the result in k1. VEX.L0.0F.W1 90 /r KMOVQ k1, k2/m64RMV/VAVX512BWMove 64 bits mask from k2/m64 and store the result in k1.VEX.L0.66.0F.W1 90 /r KMOVD k1, k2/m32RMV/VAVX512BWMove 32 bits mask from k2/m32 and store the result in k1. VEX.L0.0F.W0 91 /r KMOVW m16, k1MRV/VAVX512FMove 16 bits mask from k1 and store the result in m16.VEX.L0.66.0F.W0 91 /r KMOVB m8, k1MRV/VAVX512DQMove 8 bits mask from k1 and store the result in m8. VEX.L0.0F.W1 91 /r KMOVQ m64, k1MRV/VAVX512BWMove 64 bits mask from k1 and store the result in m64.VEX.L0.66.0F.W1 91 /r KMOVD m32, k1MRV/VAVX512BWMove 32 bits mask from k1 and store the result in m32.VEX.L0.0F.W0 92 /r KMOVW k1, r32RRV/VAVX512FMove 16 bits mask from r32 to k1.VEX.L0.66.0F.W0 92 /r KMOVB k1, r32RRV/VAVX512DQMove 8 bits mask from r32 to k1.VEX.L0.F2.0F.W1 92 /r KMOVQ k1, r64RRV/IAVX512BWMove 64 bits mask from r64 to k1.VEX.L0.F2.0F.W0 92 /r KMOVD k1, r32RRV/VAVX512BWMove 32 bits mask from r32 to k1.VEX.L0.0F.W0 93 /r KMOVW r32, k1RRV/VAVX512FMove 16 bits mask from k1 to r32.VEX.L0.66.0F.W0 93 /r KMOVB r32, k1RRV/VAVX512DQMove 8 bits mask from k1 to r32.VEX.L0.F2.0F.W1 93 /r KMOVQ r64, k1RRV/IAVX512BWMove 64 bits mask from k1 to r64.VEX.L0.F2.0F.W0 93 /r KMOVD r32, k1RRV/VAVX512BWMove 32 bits mask from k1 to r32.Op/EnOperand 1Operand 2RMModRM:reg (w)ModRM:r/m (r)MRModRM:r/m (w, ModRM:[7:6] must not be 11b)ModRM:reg (r)RRModRM:reg (w)ModRM:r/m (r, ModRM:[7:6] must be 11b)

image/svg+xmlOperationKMOVWIF *destination is a memory location*DEST[15:0] := SRC[15:0]IF *destination is a mask register or a GPR *DEST := ZeroExtension(SRC[15:0])KMOVBIF *destination is a memory location*DEST[7:0] := SRC[7:0]IF *destination is a mask register or a GPR *DEST := ZeroExtension(SRC[7:0])KMOVQIF *destination is a memory location or a GPR*DEST[63:0] := SRC[63:0]IF *destination is a mask register*DEST := ZeroExtension(SRC[63:0])KMOVDIF *destination is a memory location*DEST[31:0] := SRC[31:0]IF *destination is a mask register or a GPR *DEST := ZeroExtension(SRC[31:0])Intel C/C++ Compiler Intrinsic EquivalentKMOVW __mmask16 _mm512_kmov(__mmask16 a);Flags AffectedNoneSIMD Floating-Point ExceptionsNoneOther ExceptionsInstructions with RR operand encoding, see Table2-63, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg)”.Instructions with RM or MR operand encoding, see Table2-64, “TYPE K21 Exception Definition (VEX-Encoded OpMask Instructions Addressing Memory)”.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.