KANDW/KANDB/KANDQ/KANDD—Bitwise Logical AND MasksInstruction Operand EncodingDescriptionPerforms a bitwise AND between the vector mask k2 and the vector mask k3, and writes the result into vector mask k1.OperationKANDWDEST[15:0] := SRC1[15:0] BITWISE AND SRC2[15:0]DEST[MAX_KL-1:16] := 0KANDBDEST[7:0] := SRC1[7:0] BITWISE AND SRC2[7:0]DEST[MAX_KL-1:8] := 0KANDQDEST[63:0] := SRC1[63:0] BITWISE AND SRC2[63:0]DEST[MAX_KL-1:64] := 0KANDDDEST[31:0] := SRC1[31:0] BITWISE AND SRC2[31:0]DEST[MAX_KL-1:32] := 0Intel C/C++ Compiler Intrinsic EquivalentKANDW __mmask16 _mm512_kand(__mmask16 a, __mmask16 b);Flags AffectedNoneSIMD Floating-Point ExceptionsNoneOther ExceptionsSee Table2-63, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg)”.Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionVEX.L1.0F.W0 41 /r KANDW k1, k2, k3RVRV/VAVX512FBitwise AND 16 bits masks k2 and k3 and place result in k1.VEX.L1.66.0F.W0 41 /r KANDB k1, k2, k3RVRV/VAVX512DQBitwise AND 8 bits masks k2 and k3 and place result in k1. VEX.L1.0F.W1 41 /r KANDQ k1, k2, k3RVRV/VAVX512BWBitwise AND 64 bits masks k2 and k3 and place result in k1.VEX.L1.66.0F.W1 41 /r KANDD k1, k2, k3RVRV/VAVX512BWBitwise AND 32 bits masks k2 and k3 and place result in k1. Op/EnOperand 1Operand 2Operand 3RVRModRM:reg (w)VEX.1vvv (r)ModRM:r/m (r, ModRM:[7:6] must be 11b)
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