image/svg+xmlKANDNW/KANDNB/KANDNQ/KANDND—Bitwise Logical AND NOT MasksInstruction Operand EncodingDescriptionPerforms a bitwise AND NOT between the vector mask k2 and the vector mask k3, and writes the result into vector mask k1.OperationKANDNWDEST[15:0] := (BITWISE NOT SRC1[15:0]) BITWISE AND SRC2[15:0]DEST[MAX_KL-1:16] := 0KANDNBDEST[7:0] := (BITWISE NOT SRC1[7:0]) BITWISE AND SRC2[7:0]DEST[MAX_KL-1:8] := 0KANDNQDEST[63:0] := (BITWISE NOT SRC1[63:0]) BITWISE AND SRC2[63:0]DEST[MAX_KL-1:64] := 0KANDNDDEST[31:0] := (BITWISE NOT SRC1[31:0]) BITWISE AND SRC2[31:0]DEST[MAX_KL-1:32] := 0Intel C/C++ Compiler Intrinsic EquivalentKANDNW __mmask16 _mm512_kandn(__mmask16 a, __mmask16 b);Flags AffectedNoneSIMD Floating-Point ExceptionsNoneOther ExceptionsSee Table2-63, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg)”.Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionVEX.L1.0F.W0 42 /r KANDNW k1, k2, k3RVRV/VAVX512FBitwise AND NOT 16 bits masks k2 and k3 and place result in k1.VEX.L1.66.0F.W0 42 /r KANDNB k1, k2, k3RVRV/VAVX512DQBitwise AND NOT 8 bits masks k1 and k2 and place result in k1.VEX.L1.0F.W1 42 /r KANDNQ k1, k2, k3RVRV/VAVX512BWBitwise AND NOT 64 bits masks k2 and k3 and place result in k1.VEX.L1.66.0F.W1 42 /r KANDND k1, k2, k3RVRV/VAVX512BWBitwise AND NOT 32 bits masks k2 and k3 and place result in k1.Op/EnOperand 1Operand 2Operand 3RVRModRM:reg (w)VEX.1vvv (r)ModRM:r/m (r, ModRM:[7:6] must be 11b)

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