image/svg+xml KADDW/KADDB/KADDQ/KADDD—ADD Two Masks Instruction Operand Encoding Description Adds the vector mask k2 and the vector mask k3, and writes the result into vector mask k1. Operation KADDW DEST[15:0] := SRC1[15:0] + SRC2[15:0] DEST[MAX_KL-1:16] := 0 KADDB DEST[7:0] := SRC1[7:0] + SRC2[7:0] DEST[MAX_KL-1:8] := 0 KADDQ DEST[63:0] := SRC1[63:0] + SRC2[63:0] DEST[MAX_KL-1:64] := 0 KADDD DEST[31:0] := SRC1[31:0] + SRC2[31:0] DEST[MAX_KL-1:32] := 0 Intel C/C++ Compiler Intrinsic Equivalent SIMD Floating-Point Exceptions None Other Exceptions See Table2-63, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg)”. Opcode/ Instruction Op/En64/32 bit Mode Support CPUID Feature Flag Description VEX.L1.0F.W0 4A /r KADDW k1, k2, k3 RVRV/VAVX512DQAdd 16 bits masks in k2 and k3 and place result in k1. VEX.L1.66.0F.W0 4A /r KADDB k1, k2, k3 RVRV/VAVX512DQAdd 8 bits masks in k2 and k3 and place result in k1. VEX.L1.0F.W1 4A /r KADDQ k1, k2, k3 RVRV/VAVX512BWAdd 64 bits masks in k2 and k3 and place result in k1. VEX.L1.66.0F.W1 4A /r KADDD k1, k2, k3 RVRV/VAVX512BWAdd 32 bits masks in k2 and k3 and place result in k1. Op/EnOperand 1Operand 2Operand 3 RVRModRM:reg (w)VEX.1vvv (r)ModRM:r/m (r, ModRM:[7:6] must be 11b) This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .