INVPCID—Invalidate Process-Context IdentifierInstruction Operand EncodingDescriptionInvalidates mappings in the translation lookaside buffers (TLBs) and paging-structure caches based on process-context identifier (PCID). (See Section 4.10, “Caching Translation Information,” in Intel64 and IA-32 Architecture Software Developer’s Manual, Volume 3A.) Invalidation is based on the INVPCID type specified in the register operand and the INVPCID descriptor specified in the memory operand.Outside 64-bit mode, the register operand is always 32 bits, regardless of the value of CS.D. In 64-bit mode the register operand has 64 bits.There are four INVPCID types currently defined:•Individual-address invalidation: If the INVPCID type is 0, the logical processor invalidates mappings—except global translations—for the linear address and PCID specified in the INVPCID descriptor.1 In some cases, the instruction may invalidate global translations or mappings for other linear addresses (or other PCIDs) as well.•Single-context invalidation: If the INVPCID type is 1, the logical processor invalidates all mappings—except global translations—associated with the PCID specified in the INVPCID descriptor. In some cases, the instruction may invalidate global translations or mappings for other PCIDs as well.•All-context invalidation, including global translations: If the INVPCID type is 2, the logical processor invalidates all mappings—including global translations—associated with any PCID. •All-context invalidation: If the INVPCID type is 3, the logical processor invalidates all mappings—except global translations—associated with any PCID. In some case, the instruction may invalidate global translations as well. The INVPCID descriptor comprises 128 bits and consists of a PCID and a linear address as shown in Figure 3-24. For INVPCID type 0, the processor uses the full 64 bits of the linear address even outside 64-bit mode; the linear address is not used for other INVPCID types.Opcode/InstructionOp/ En64/32-bit ModeCPUID Feature FlagDescription66 0F 38 82 /rINVPCID r32, m128RMNE/VINVPCIDInvalidates entries in the TLBs and paging-structure caches based on invalidation type in r32 and descrip-tor in m128.66 0F 38 82 /rINVPCID r64, m128RMV/NEINVPCIDInvalidates entries in the TLBs and paging-structure caches based on invalidation type in r64 and descrip-tor in m128.Op/EnOperand 1Operand 2Operand 3Operand 4RMModRM:reg (r)ModRM:r/m (r)NANA1.If the paging structures map the linear address using a page larger than 4 KBytes and there are multiple TLB entries for that page (see Section 4.10.2.3, “Details of TLB Use,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A), the instruction invalidates all of them.Figure 3-24. INVPCID Descriptor127646301112Reserved (must be zero)Linear AddressPCID
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