image/svg+xmlINCSSPD/INCSSPQ—Increment Shadow Stack PointerInstruction Operand EncodingDescriptionThis instruction can be used to increment the current shadow stack pointer by the operand size of the instruction times the unsigned 8-bit value specified by bits 7:0 in the source operand. The instruction performs a pop and discard of the first and last element on the shadow stack in the range specified by the unsigned 8-bit value in bits 7:0 of the source operand.OperationIF CPL = 3IF (CR4.CET & IA32_U_CET.SH_STK_EN) = 0THEN #UD; FI;ELSEIF (CR4.CET & IA32_S_CET.SH_STK_EN) = 0THEN #UD; FI;FI;IF (operand size is 64-bit)THENTMP1 = (R64[7:0] == 0) ? 1 : R64[7:0]TMP = ShadowStackLoad8B(SSP)TMP = ShadowStackLoad8B(SSP + TMP1 * 8 - 8)SSP := SSP + R64[7:0] * 8;ELSETMP1 = (R32[7:0] == 0) ? 1 : R32[7:0]TMP = ShadowStackLoad4B(SSP)TMP = ShadowStackLoad4B(SSP + TMP1 * 4 - 4)SSP := SSP + R32[7:0] * 4;FI;Flags AffectedNone.Intel C/C++ Compiler Intrinsic EquivalentINCSSPDvoid _incsspd(int);INCSSPQvoid _incsspq(int);Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionF3 0F AE /05INCSSPD r32RV/VCET_SSIncrement SSP by 4 * r32[7:0].F3 REX.W 0F AE /05INCSSPQ r64RV/N.E.CET_SSIncrement SSP by 8 * r64[7:0].Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4RNAModRM:r/m (r)NANANA

image/svg+xmlProtected Mode Exceptions#UDIf the LOCK prefix is used.If CR4.CET = 0.IF CPL = 3 and IA32_U_CET.SH_STK_EN = 0.IF CPL < 3 and IA32_S_CET.SH_STK_EN = 0.#PF(fault-code)If a page fault occurs.Real-Address Mode Exceptions#UD The INCSSP instruction is not recognized in real-address mode.Virtual-8086 Mode Exceptions#UD The INCSSP instruction is not recognized in virtual-8086 mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.

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