image/svg+xmlINC—Increment by 1Instruction Operand EncodingDescriptionAdds 1 to the destination operand, while preserving the state of the CF flag. The destination operand can be a register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag. (Use a ADD instruction with an immediate operand of 1 to perform an increment operation that does updates the CF flag.)This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.In 64-bit mode, INC r16 and INC r32 are not encodable (because opcodes 40H through 47H are REX prefixes). Otherwise, the instruction’s 64-bit mode default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits.OperationDEST := DEST + 1;Flags AffectedThe CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.Protected Mode Exceptions#GP(0)If the destination operand is located in a non-writable segment.If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and it contains a NULLsegment selector.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used but the destination is not a memory operand.OpcodeInstructionOp/ En64-Bit ModeCompat/Leg ModeDescriptionFE /0INC r/m8MValidValidIncrement r/m byte by 1.REX + FE /0INC r/m8*MValidN.E.Increment r/m byte by 1.FF /0INC r/m16MValidValidIncrement r/m word by 1.FF /0INC r/m32MValidValidIncrement r/m doubleword by 1.REX.W + FF /0INC r/m64MValidN.E.Increment r/m quadword by 1.40+ rw**INC r16ON.E.ValidIncrement word register by 1.40+ rdINC r32ON.E.ValidIncrement doubleword register by 1.NOTES:*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.**40H through 47H are REX prefixes in 64-bit mode.Op/EnOperand 1Operand 2Operand 3Operand 4MModRM:r/m (r, w)NANANAOopcode + rd (r, w)NANANA

image/svg+xmlReal-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SS segment limit.#UD If the LOCK prefix is used but the destination is not a memory operand.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made.#UD If the LOCK prefix is used but the destination is not a memory operand.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used but the destination is not a memory operand.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.