IMUL—Signed MultiplyInstruction Operand EncodingDescriptionPerforms a signed multiplication of two operands. This instruction has three forms, depending on the number of operands. •One-operand form — This form is identical to that used by the MUL instruction. Here, the source operand (in a general-purpose register or memory location) is multiplied by the value in the AL, AX, EAX, or RAX register (depending on the operand size) and the product (twice the size of the input operand) is stored in the AX, DX:AX, EDX:EAX, or RDX:RAX registers, respectively.•Two-operand form — With this form the destination operand (the first operand) is multiplied by the source operand (second operand). The destination operand is a general-purpose register and the source operand is an immediate value, a general-purpose register, or a memory location. The intermediate product (twice the size of the input operand) is truncated and stored in the destination operand location.•Three-operand form — This form requires a destination operand (the first operand) and two source operands (the second and the third operands). Here, the first source operand (which can be a general-purpose register or a memory location) is multiplied by the second source operand (an immediate value). The intermediate product (twice the size of the first source operand) is truncated and stored in the destination operand (a general-purpose register).OpcodeInstructionOp/ En64-Bit ModeCompat/Leg ModeDescriptionF6 /5IMUL r/m8*MValidValidAX:= AL ∗r/m byte.F7 /5IMUL r/m16MValidValidDX:AX := AX ∗r/m word.F7 /5IMUL r/m32MValidValidEDX:EAX := EAX ∗r/m32.REX.W + F7 /5IMUL r/m64MValidN.E.RDX:RAX := RAX ∗r/m64.0F AF /rIMUL r16, r/m16RMValidValidword register := word register ∗r/m16.0F AF /rIMUL r32, r/m32RMValidValiddoubleword register := doubleword register ∗r/m32.REX.W + 0F AF /rIMUL r64, r/m64RMValidN.E.Quadword register := Quadword register ∗r/m64.6B /r ibIMUL r16, r/m16, imm8RMIValidValidword register := r/m16∗ sign-extended immediate byte.6B /r ibIMUL r32, r/m32, imm8RMIValidValiddoubleword register := r/m32∗ sign-extended immediate byte.REX.W + 6B /r ibIMUL r64, r/m64, imm8RMIValidN.E.Quadword register := r/m64∗ sign-extended immediate byte.69 /r iwIMUL r16, r/m16, imm16RMIValidValidword register := r/m16∗ immediate word.69 /r idIMUL r32, r/m32, imm32RMIValidValiddoubleword register := r/m32∗ immediate doubleword.REX.W + 69 /r idIMUL r64, r/m64, imm32RMIValidN.E.Quadword register := r/m64∗ immediate doubleword.NOTES:*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.Op/EnOperand 1Operand 2Operand 3Operand 4MModRM:r/m (r, w)NANANARMModRM:reg (r, w)ModRM:r/m (r)NANARMIModRM:reg (r, w)ModRM:r/m (r)imm8/16/32NA
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