image/svg+xmlHSUBPS—Packed Single-FP Horizontal SubtractInstruction Operand EncodingDescriptionSubtracts the single-precision floating-point value in the second dword of the destination operand from the first dword of the destination operand and stores the result in the first dword of the destination operand. Subtracts the single-precision floating-point value in the fourth dword of the destination operand from the third dword of the destination operand and stores the result in the second dword of the destination operand. Subtracts the single-precision floating-point value in the second dword of the source operand from the first dword of the source operand and stores the result in the third dword of the destination operand. Subtracts the single-precision floating-point value in the fourth dword of the source operand from the third dword of the source operand and stores the result in the fourth dword of the destination operand. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).See Figure3-22 for HSUBPS; see Figure3-23 for VHSUBPS.Opcode/InstructionOp/ En64/32-bit ModeCPUID Feature FlagDescriptionF2 0F 7D /rHSUBPS xmm1, xmm2/m128RMV/VSSE3Horizontal subtract packed single-precision floating-point values from xmm2/m128 to xmm1.VEX.128.F2.0F.WIG 7D /rVHSUBPS xmm1, xmm2, xmm3/m128RVMV/VAVXHorizontal subtract packed single-precision floating-point values from xmm2 and xmm3/mem.VEX.256.F2.0F.WIG 7D /rVHSUBPS ymm1, ymm2, ymm3/m256RVMV/VAVXHorizontal subtract packed single-precision floating-point values from ymm2 and ymm3/mem.Op/EnOperand 1Operand 2Operand 3Operand 4RMModRM:reg (r, w)ModRM:r/m (r)NANARVMModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlFigure 3-23. VHSUBPS operation128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding YMM register destination are unmodified.VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are zeroed.VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register. Figure 3-22. HSUBPS—Packed Single-FP Horizontal SubtractOM15996HSUBPS xmm1, xmm2/m128RESULT:xmm1xmm2/m128xmm1[31:0] - xmm1[63:32][31:0]xmm1[95:64] - xmm1[127:96][63:32][63:32][31:0]xmm1[31:0][63:32]xmm2/m128[31:0] - xmm2/m128[63:32][95:64]xmm2/m128[95:64] - xmm2/m128[127:96][127:96][127:96][95:64][95:64][127:96]Y6-Y7X6-X7Y2-Y3X2-X3DESTSRC1X0SRC2X1X2X3X4X5X6X7Y0Y1Y2Y3Y4Y5Y6Y7X0-X1Y4-Y5X4-X5Y0-Y1

image/svg+xmlOperationHSUBPS (128-bit Legacy SSE version)DEST[31:0] := SRC1[31:0] - SRC1[63:32]DEST[63:32] := SRC1[95:64] - SRC1[127:96]DEST[95:64] := SRC2[31:0] - SRC2[63:32]DEST[127:96] := SRC2[95:64] - SRC2[127:96] DEST[MAXVL-1:128] (Unmodified)VHSUBPS (VEX.128 encoded version)DEST[31:0] := SRC1[31:0] - SRC1[63:32]DEST[63:32] := SRC1[95:64] - SRC1[127:96]DEST[95:64] := SRC2[31:0] - SRC2[63:32]DEST[127:96] := SRC2[95:64] - SRC2[127:96] DEST[MAXVL-1:128] := 0VHSUBPS (VEX.256 encoded version)DEST[31:0] := SRC1[31:0] - SRC1[63:32]DEST[63:32] := SRC1[95:64] - SRC1[127:96]DEST[95:64] := SRC2[31:0] - SRC2[63:32]DEST[127:96] := SRC2[95:64] - SRC2[127:96] DEST[159:128] := SRC1[159:128] - SRC1[191:160]DEST[191:160] := SRC1[223:192] - SRC1[255:224]DEST[223:192] := SRC2[159:128] - SRC2[191:160]DEST[255:224] := SRC2[223:192] - SRC2[255:224]Intel C/C++ Compiler Intrinsic EquivalentHSUBPS:__m128 _mm_hsub_ps(__m128 a, __m128 b);VHSUBPS:__m256 _mm256_hsub_ps (__m256 a, __m256 b);ExceptionsWhen the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.Numeric ExceptionsOverflow, Underflow, Invalid, Precision, DenormalOther ExceptionsSee Table2-19, “Type 2 Class Exception Conditions”.

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