image/svg+xmlHSUBPD—Packed Double-FP Horizontal SubtractInstruction Operand EncodingDescriptionThe HSUBPD instruction subtracts horizontally the packed DP FP numbers of both operands. Subtracts the double-precision floating-point value in the high quadword of the destination operand from the low quadword of the destination operand and stores the result in the low quadword of the destination operand. Subtracts the double-precision floating-point value in the high quadword of the source operand from the low quad-word of the source operand and stores the result in the high quadword of the destination operand. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).See Figure3-20 for HSUBPD; see Figure3-21 for VHSUBPD.Opcode/InstructionOp/ En64/32-bit ModeCPUID Feature FlagDescription66 0F 7D /rHSUBPD xmm1, xmm2/m128RMV/VSSE3Horizontal subtract packed double-precision floating-point values from xmm2/m128 to xmm1.VEX.128.66.0F.WIG 7D /rVHSUBPD xmm1,xmm2, xmm3/m128RVMV/VAVXHorizontal subtract packed double-precision floating-point values from xmm2 and xmm3/mem.VEX.256.66.0F.WIG 7D /rVHSUBPD ymm1, ymm2, ymm3/m256RVMV/VAVXHorizontal subtract packed double-precision floating-point values from ymm2 and ymm3/mem.Op/EnOperand 1Operand 2Operand 3Operand 4RMModRM:reg (r, w)ModRM:r/m (r)NANARVMModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NAFigure 3-20. HSUBPD—Packed Double-FP Horizontal SubtractOM15995HSUBPD xmm1, xmm2/m128xmm1xmm2/m128[63:0][127:64][127:64][63:0][63:0][127:64]Result:xmm1xmm2/m128[63:0] -xmm2/m128[127:64]xmm1[63:0] - xmm1[127:64]

image/svg+xmlFigure 3-21. VHSUBPD operation128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding YMM register destination are unmodified.VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are zeroed.VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register. OperationHSUBPD (128-bit Legacy SSE version)DEST[63:0] := SRC1[63:0] - SRC1[127:64] DEST[127:64] := SRC2[63:0] - SRC2[127:64] DEST[MAXVL-1:128] (Unmodified)VHSUBPD (VEX.128 encoded version)DEST[63:0] := SRC1[63:0] - SRC1[127:64] DEST[127:64] := SRC2[63:0] - SRC2[127:64] DEST[MAXVL-1:128] := 0VHSUBPD (VEX.256 encoded version)DEST[63:0] := SRC1[63:0] - SRC1[127:64] DEST[127:64] := SRC2[63:0] - SRC2[127:64] DEST[191:128] := SRC1[191:128] - SRC1[255:192]DEST[255:192] := SRC2[191:128] - SRC2[255:192]Intel C/C++ Compiler Intrinsic EquivalentHSUBPD:__m128d _mm_hsub_pd(__m128d a, __m128d b)VHSUBPD:__m256d _mm256_hsub_pd (__m256d a, __m256d b);ExceptionsWhen the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.Numeric ExceptionsOverflow, Underflow, Invalid, Precision, DenormalY2 - Y3X2 - X3Y0 - Y1X0 - X1DESTX3X2SRC1X1X0Y3Y2Y1Y0SRC2

image/svg+xmlOther ExceptionsSee Table2-19, “Type 2 Class Exception Conditions”.

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