image/svg+xmlHRESET — History ResetInstruction Operand EncodingDescriptionRequests the processor to selectively reset selected components of hardware history maintained by the current logical processor. HRESET operation is controlled by the implicit EAX operand. The value of the explicit imm8 operand is ignored. This instruction can only be executed at privilege level 0.The HRESET instruction can be used to request reset of multiple components of hardware history. Prior to the execution of HRESET, the system software must take the following steps:1.Enumerate the HRESET capabilities via CPUID.20H.0H:EBX, which indicates what components of hardware history can be reset.2.Only the bits enumerated by CPUID.20H.0H:EBX can be set in the IA32_HRESET_ENABLE MSR. HRESET causes a general-protection exception (#GP) if EAX sets any bits that are not set in the IA32_HRESET_ENABLE MSR. Any attempt to execute the HRESET instruction inside a transactional region will result in a transaction abort.OperationIF EAX = 0 THEN NOP ELSE FOREACH i such that EAX[i] = 1 Reset prediction history for feature iFIFlags AffectedNone.Protected Mode Exceptions#GP(0) If CPL > 0 or (EAX AND NOT IA32_HRESET_ENABLE) ≠0.#UD If CPUID.07H.01H:EAX.HRESET[bit 22] = 0.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode Exceptions#GP(0) HRESET instruction is not recognized in virtual-8086 mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionF3 0F 3A F0 C0 /ib HRESET imm8, <EAX> AV/VHRESETProcessor history reset request. Controlled by the EAX implicit operand.Op/EnTupleOperand 1Operand 2Operand 3Operand 4ANAModRM:r/m (r)NANANA

image/svg+xml64-Bit Mode ExceptionsSame exceptions as in protected mode.

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