image/svg+xmlHADDPD—Packed Double-FP Horizontal AddInstruction Operand EncodingDescriptionAdds the double-precision floating-point values in the high and low quadwords of the destination operand and stores the result in the low quadword of the destination operand. Adds the double-precision floating-point values in the high and low quadwords of the source operand and stores the result in the high quadword of the destination operand. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).See Figure3-16 for HADDPD; see Figure3-17 for VHADDPD.Opcode/InstructionOp/ En64/32-bit ModeCPUID Feature FlagDescription66 0F 7C /rHADDPD xmm1, xmm2/m128RMV/VSSE3Horizontal add packed double-precision floating-point values from xmm2/m128 to xmm1.VEX.128.66.0F.WIG 7C /rVHADDPD xmm1,xmm2, xmm3/m128RVMV/VAVXHorizontal add packed double-precision floating-point values from xmm2 and xmm3/mem.VEX.256.66.0F.WIG 7C /rVHADDPD ymm1, ymm2, ymm3/m256RVMV/VAVXHorizontal add packed double-precision floating-point values from ymm2 and ymm3/mem.Op/EnOperand 1Operand 2Operand 3Operand 4RMModRM:reg (r, w)ModRM:r/m (r)NANARVMModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NAFigure 3-16. HADDPD—Packed Double-FP Horizontal AddOM15993HADDPD xmm1, xmm2/m128xmm1xmm2/m128[63:0][127:64][127:64][63:0][63:0][127:64]Result:xmm1xmm2/m128[63:0] +xmm2/m128[127:64]xmm1[63:0] + xmm1[127:64]

image/svg+xmlFigure 3-17. VHADDPD operation128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding YMM register destination are unmodified.VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are zeroed.VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register. OperationHADDPD (128-bit Legacy SSE version)DEST[63:0] := SRC1[127:64] + SRC1[63:0]DEST[127:64] := SRC2[127:64] + SRC2[63:0]DEST[MAXVL-1:128] (Unmodified)VHADDPD (VEX.128 encoded version)DEST[63:0] := SRC1[127:64] + SRC1[63:0]DEST[127:64] := SRC2[127:64] + SRC2[63:0]DEST[MAXVL-1:128] := 0VHADDPD (VEX.256 encoded version)DEST[63:0] := SRC1[127:64] + SRC1[63:0]DEST[127:64] := SRC2[127:64] + SRC2[63:0]DEST[191:128] := SRC1[255:192] + SRC1[191:128]DEST[255:192] := SRC2[255:192] + SRC2[191:128]Intel C/C++ Compiler Intrinsic EquivalentVHADDPD:__m256d _mm256_hadd_pd (__m256d a, __m256d b);HADDPD:__m128d _mm_hadd_pd (__m128d a, __m128d b);ExceptionsWhen the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. Y2 + Y3X2 + X3Y0 + Y1X0 + X1DESTX3X2SRC1X1X0Y3Y2Y1Y0SRC2

image/svg+xmlNumeric ExceptionsOverflow, Underflow, Invalid, Precision, DenormalOther ExceptionsSee Table2-19, “Type 2 Class Exception Conditions”.

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