image/svg+xmlGF2P8AFFINEINVQB—Galois Field Affine Transformation InverseInstruction Operand EncodingDescriptionThe AFFINEINVB instruction computes an affine transformation in the Galois Field 28. For this instruction, an affine transformation is defined by A * inv(x) + b where “A” is an 8 by 8 bit matrix, and “x” and “b” are 8-bit vectors. The inverse of the bytes in x is defined with respect to the reduction polynomial x8 + x4 + x3 + x + 1.One SIMD register (operand 1) holds “x” as either 16, 32 or 64 8-bit vectors. A second SIMD (operand 2) register or memory operand contains 2, 4, or 8 “A” values, which are operated upon by the correspondingly aligned 8 “x” values in the first register. The “b” vector is constant for all calculations and contained in the immediate byte.The EVEX encoded form of this instruction does not support memory fault suppression. The SSE encoded forms of the instruction require 16B alignment on their memory operations.The inverse of each byte is given by the following table. The upper nibble is on the vertical axis and the lower nibble is on the horizontal axis. For example, the inverse of 0x95 is 0x8A.Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription66 0F3A CF /r /ibGF2P8AFFINEINVQB xmm1, xmm2/m128, imm8AV/VGFNIComputes inverse affine transformation in the finite field GF(2^8).VEX.128.66.0F3A.W1 CF /r /ibVGF2P8AFFINEINVQB xmm1, xmm2, xmm3/m128, imm8BV/VAVXGFNIComputes inverse affine transformation in the finite field GF(2^8).VEX.256.66.0F3A.W1 CF /r /ibVGF2P8AFFINEINVQB ymm1, ymm2, ymm3/m256, imm8BV/VAVXGFNIComputes inverse affine transformation in the finite field GF(2^8).EVEX.128.66.0F3A.W1 CF /r /ibVGF2P8AFFINEINVQB xmm1{k1}{z}, xmm2, xmm3/m128/m64bcst, imm8CV/VAVX512VLGFNIComputes inverse affine transformation in the finite field GF(2^8).EVEX.256.66.0F3A.W1 CF /r /ibVGF2P8AFFINEINVQB ymm1{k1}{z}, ymm2, ymm3/m256/m64bcst, imm8CV/VAVX512VLGFNIComputes inverse affine transformation in the finite field GF(2^8).EVEX.512.66.0F3A.W1 CF /r /ibVGF2P8AFFINEINVQB zmm1{k1}{z}, zmm2, zmm3/m512/m64bcst, imm8CV/VAVX512FGFNIComputes inverse affine transformation in the finite field GF(2^8).Op/EnTupleOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)imm8 (r)NABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)imm8 (r)CFullModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)imm8 (r)

image/svg+xmlOperationdefine affine_inverse_byte(tsrc2qw, src1byte, imm):FOR i := 0 to 7:* parity(x) = 1 if x has an odd number of 1s in it, and 0 otherwise.** inverse(x) is defined in the table above *retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]return retbyteVGF2P8AFFINEINVQB dest, src1, src2, imm8 (EVEX encoded version)(KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1:IF SRC2 is memory and EVEX.b==1:tsrc2 := SRC2.qword[0]ELSE:tsrc2 := SRC2.qword[j]FOR b := 0 to 7:IF k1[j*8+b] OR *no writemask*:FOR i := 0 to 7:DEST.qword[j].byte[b] := affine_inverse_byte(tsrc2, SRC1.qword[j].byte[b], imm8)ELSE IF *zeroing*:DEST.qword[j].byte[b] := 0*ELSE DEST.qword[j].byte[b] remains unchanged*DEST[MAX_VL-1:VL] := 0Table 3-50. Inverse Byte Listings-0123456789ABCDEF0018DF6CB527BD1E84F29C0B0E1E5C7174B4AA4B992B605F583FFDCCFF40EEB223A6E5AF1554DA8C9C1A98153044A2C232C45926CF3396642F235206F77BB591941DFE37672D31F569A764AB135425E995ED5C5CA4C2487BF183E22F051EC61176165EAFD349A63643F44791DF3393213B779B7978510B5BA3CB670D06A1FA81828837E7F809673BE569B9E95D9F72B9A49DE6A326DD88A84722A149F88F9DC899AAFB7C2EC38FB8654826C8124ACEE7D262BCE01FEF11757871A58E763DBDBC8657CB282FA3DAD4E4FA9275341BFCACE6D7A7AE63C5DBE2EA948BC4D59DF8906BEB1DD6EBC6ECFAD84ED7E35D501EB3F5B233834684638CDD9C7DA0CD1A411C

image/svg+xmlVGF2P8AFFINEINVQB dest, src1, src2, imm8 (128b and 256b VEX encoded versions)(KL, VL) = (2, 128), (4, 256)FOR j := 0 TO KL-1:FOR b := 0 to 7:DEST.qword[j].byte[b] := affine_inverse_byte(SRC2.qword[j], SRC1.qword[j].byte[b], imm8)DEST[MAX_VL-1:VL] := 0GF2P8AFFINEINVQB srcdest, src1, imm8 (128b SSE encoded version)FOR j := 0 TO 1:FOR b := 0 to 7:SRCDEST.qword[j].byte[b] := affine_inverse_byte(SRC1.qword[j], SRCDEST.qword[j].byte[b], imm8)Intel C/C++ Compiler Intrinsic Equivalent(V)GF2P8AFFINEINVQB __m128i _mm_gf2p8affineinv_epi64_epi8(__m128i, __m128i, int);(V)GF2P8AFFINEINVQB __m128i _mm_mask_gf2p8affineinv_epi64_epi8(__m128i, __mmask16, __m128i, __m128i, int);(V)GF2P8AFFINEINVQB __m128i _mm_maskz_gf2p8affineinv_epi64_epi8(__mmask16, __m128i, __m128i, int);VGF2P8AFFINEINVQB __m256i _mm256_gf2p8affineinv_epi64_epi8(__m256i, __m256i, int);VGF2P8AFFINEINVQB __m256i _mm256_mask_gf2p8affineinv_epi64_epi8(__m256i, __mmask32, __m256i, __m256i, int);VGF2P8AFFINEINVQB __m256i _mm256_maskz_gf2p8affineinv_epi64_epi8(__mmask32, __m256i, __m256i, int);VGF2P8AFFINEINVQB __m512i _mm512_gf2p8affineinv_epi64_epi8(__m512i, __m512i, int);VGF2P8AFFINEINVQB __m512i _mm512_mask_gf2p8affineinv_epi64_epi8(__m512i, __mmask64, __m512i, __m512i, int);VGF2P8AFFINEINVQB __m512i _mm512_maskz_gf2p8affineinv_epi64_epi8(__mmask64, __m512i, __m512i, int);SIMD Floating-Point ExceptionsNone.Other ExceptionsLegacy-encoded and VEX-encoded: See Table2-21, “Type 4 Class Exception Conditions”.EVEX-encoded: See Table2-50, “Type E4NF Class Exception Conditions”.

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