image/svg+xml FYL2XP1—Compute y ∗ log 2 (x + 1) Description Computes (ST(1) ∗ log 2 (ST(0) + 1.0)), stores the result in register ST(1), and pops the FPU register stack. The source operand in ST(0) must be in the range: The source operand in ST(1) can range from −∞ to +∞ . If the ST(0) operand is outside of its acceptable range, the result is undefined and software should not rely on an exception being generated. Under some circumstances exceptions may be generated when ST(0) is out of range, but this behavior is implementation specific and not guaranteed. The following table shows the results obtained when taking the log epsilon of various classes of numbers, assuming that underflow does not occur. This instruction provides optimal accuracy for values of epsilon [the value in register ST(0)] that are close to 0. For small epsilon ( ε ) values, more significant digits can be retained by using the FYL2XP1 instruction than by using ( ε+ 1) as an argument to the FYL2X instruction. The ( ε+ 1) expression is commonly found in compound interest and annuity calculations. The result can be simply converted into a value in another logarithm base by including a scale factor in the ST(1) source operand. The following equation is used to calculate the scale factor for a particular loga- rithm base, where n is the logarithm base desired for the result of the FYL2XP1 instruction: scale factor := log n 2 This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Operation ST(1) := ST(1) ∗ log 2 (ST(0) + 1.0); PopRegisterStack; OpcodeInstruction64-Bit Mode Compat/ Leg Mode Description D9 F9FYL2XP1ValidValidReplace ST(1) with ST(1) ∗ log 2 (ST(0) + 1.0) and pop the register stack. Table 3-49. FYL2XP1 Results ST(0) − (1 − ( )) to − 0 -0+0 + 0 to + (1 - ())NaN − ∞ + ∞ ** − ∞ NaN ST(1) − F+F+0-0 − F NaN − 0+0+0-0 − 0 NaN +0 − 0 − 0+0+0 NaN +F − F − 0+0+F NaN + ∞ − ∞ **+ ∞ NaN NaNNaNNaNNaNNaN NaN NOTES: FMeans finite floating-point value. *Indicates floating-point invalid-operation (#IA) exception. 122 ⁄ – ()) to122 ⁄ – () – 22 ⁄ 22 ⁄ image/svg+xml FPU Flags Affected C1Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Point Exceptions #ISStack underflow occurred. #IAEither operand is an SNaN value or unsupported format. #DSource operand is a denormal value. #UResult is too small for destination format. #OResult is too large for destination format. #PValue cannot be represented exactly in destination format. Protected Mode Exceptions #NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as in protected mode. Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .