image/svg+xml FXCH—Exchange Register Contents Description Exchanges the contents of registers ST(0) and ST(i). If no source operand is specified, the contents of ST(0) and ST(1) are exchanged. This instruction provides a simple means of moving values in the FPU register stack to the top of the stack [ST(0)], so that they can be operated on by those floating-point instructions that can only operate on values in ST(0). For example, the following instruction sequence takes the square root of the third register from the top of the register stack: FXCH ST(3); FSQRT; FXCH ST(3); This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Operation IF (Number-of-operands) is 1 THEN temp := ST(0); ST(0) := SRC; SRC := temp; ELSE temp := ST(0); ST(0) := ST(1); ST(1) := temp; FI; FPU Flags Affected C1Set to 0. C0, C2, C3 Undefined. Floating-Point Exceptions #ISStack underflow occurred. Protected Mode Exceptions #NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as in protected mode. Virtual-8086 Mode Exceptions Same exceptions as in protected mode. OpcodeInstruction64-Bit Mode Compat/ Leg Mode Description D9 C8+iFXCH ST(i)ValidValidExchange the contents of ST(0) and ST(i). D9 C9FXCHValidValidExchange the contents of ST(0) and ST(1). image/svg+xml Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .