image/svg+xml FXAM—Examine Floating-Point Description Examines the contents of the ST(0) register and sets the condition code flags C0, C2, and C3 in the FPU status word to indicate the class of value or number in the register (see the table below). . The C1 flag is set to the sign of the value in ST(0), regardless of whether the register is empty or full. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Operation C1 := sign bit of ST; (* 0 for positive, 1 for negative *) CASE (class of value or number in ST(0)) OF Unsupported:C3, C2, C0 := 000; NaN:C3, C2, C0 := 001; Normal:C3, C2, C0 := 010; Infinity:C3, C2, C0 := 011; Zero:C3, C2, C0 := 100; Empty:C3, C2, C0 := 101; Denormal:C3, C2, C0 := 110; ESAC; FPU Flags Affected C1Sign of value in ST(0). C0, C2, C3See Table 3-42. Floating-Point Exceptions None Protected Mode Exceptions #NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as in protected mode. OpcodeInstruction64-Bit Mode Compat/ Leg Mode Description D9 E5FXAMValidValidClassify value or number in ST(0). Table 3-42. FXAM Results ClassC3C2C0 Unsupported 000 NaN 001 Normal finite number 010 Infinity 011 Zero 100 Empty 101 Denormal number 110 image/svg+xml Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .