image/svg+xml FTST—TEST Description Compares the value in the ST(0) register with 0.0 and sets the condition code flags C0, C2, and C3 in the FPU status word according to the results (see table below). This instruction performs an “unordered comparison.” An unordered comparison also checks the class of the numbers being compared (see “FXAM—Examine Floating-Point” in this chapter). If the value in register ST(0) is a NaN or is in an undefined format, the condition flags are set to “unordered” and the invalid operation exception is generated. The sign of zero is ignored, so that (– 0.0 := + 0.0). This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Operation CASE (relation of operands) OF Not comparable:C3, C2, C0 := 111; ST(0) > 0.0:C3, C2, C0 := 000; ST(0) < 0.0:C3, C2, C0 := 001; ST(0) = 0.0:C3, C2, C0 := 100; ESAC; FPU Flags Affected C1Set to 0. C0, C2, C3See Table 3-40. Floating-Point Exceptions #ISStack underflow occurred. #IAThe source operand is a NaN value or is in an unsupported format. #DThe source operand is a denormal value. Protected Mode Exceptions #NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as in protected mode. OpcodeInstruction64-Bit Mode Compat/ Leg Mode Description D9 E4FTSTValidValidCompare ST(0) with 0.0. Table 3-40. FTST Results ConditionC3C2C0 ST(0) > 0.0000 ST(0) < 0.0001 ST(0) = 0.0100 Unordered111 image/svg+xml Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .