image/svg+xmlFSUBR/FSUBRP/FISUBR—Reverse SubtractDescriptionSubtracts the destination operand from the source operand and stores the difference in the destination location. The destination operand is always an FPU register; the source operand can be a register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format or in word or doubleword integer format.These instructions perform the reverse operations of the FSUB, FSUBP, and FISUB instructions. They are provided to support more efficient coding.The no-operand version of the instruction subtracts the contents of the ST(1) register from the ST(0) register and stores the result in ST(1). The one-operand version subtracts the contents of the ST(0) register from the contents of a memory location (either a floating-point or an integer value) and stores the result in ST(0). The two-operand version, subtracts the contents of the ST(i) register from the ST(0) register or vice versa.The FSUBRP instructions perform the additional operation of popping the FPU register stack following the subtrac-tion. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The no-operand version of the floating-point reverse subtract instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FSUBR rather than FSUBRP.The FISUBR instructions convert an integer source operand to double extended-precision floating-point format before performing the subtraction.The following table shows the results obtained when subtracting various classes of numbers from one another, assuming that neither overflow nor underflow occurs. Here, the DEST value is subtracted from the SRC value (SRC − DEST = result).When the difference between two operands of like sign is 0, the result is +0, except for the round toward −∞ mode, in which case the result is −0. This instruction also guarantees that +0 − (−0) = +0, and that −0 − (+0) = −0. When the source operand is an integer 0, it is treated as a +0.When one operand is ∞, the result is ∞ of the expected sign. If both operands are ∞ of the same sign, an invalid-operation exception is generated.OpcodeInstruction64-Bit ModeCompat/Leg ModeDescriptionD8 /5FSUBR m32fpValidValidSubtract ST(0) from m32fp and store result in ST(0).DC /5FSUBR m64fpValidValidSubtract ST(0) from m64fp and store result in ST(0).D8 E8+iFSUBR ST(0), ST(i)ValidValidSubtract ST(0) from ST(i) and store result in ST(0).DC E0+iFSUBR ST(i), ST(0)ValidValidSubtract ST(i) from ST(0) and store result in ST(i).DE E0+iFSUBRP ST(i), ST(0)ValidValidSubtract ST(i) from ST(0), store result in ST(i), and pop register stack.DE E1FSUBRPValidValidSubtract ST(1) from ST(0), store result in ST(1), and pop register stack.DA /5FISUBR m32intValidValidSubtract ST(0) from m32int and store result in ST(0).DE /5FISUBR m16intValidValidSubtract ST(0) from m16int and store result in ST(0).

image/svg+xmlThis instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationIF Instruction = FISUBRTHENDEST := ConvertToDoubleExtendedPrecisionFP(SRC) − DEST;ELSE (* Source operand is floating-point value *)DEST := SRC − DEST; FI;IF Instruction = FSUBRP THEN PopRegisterStack; FI;FPU Flags AffectedC1Set to 0 if stack underflow occurred.Set if result was rounded up; cleared otherwise.C0, C2, C3 Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IAOperand is an SNaN value or unsupported format.Operands are infinities of like sign.#DSource operand is a denormal value.#UResult is too small for destination format.#OResult is too large for destination format.#PValue cannot be represented exactly in destination format.Table 3-39. FSUBR/FSUBRP/FISUBR ResultsSRC− ∞−F or −I−0+0+F or +I+ ∞NaN− ∞*+ ∞+ ∞+ ∞+ ∞+ ∞NaN− F− ∞±F or ±0−DEST−DEST+ F+ ∞NaNDEST− 0− ∞SRC±0+ 0SRC+ ∞NaN+ 0− ∞SRC− 0±0SRC+ ∞NaN+ F− ∞− F−DEST−DEST±F or ±0+ ∞NaN+ ∞− ∞− ∞− ∞− ∞− ∞*NaNNaNNaNNaNNaNNaNNaNNaNNaNNOTES:FMeans finite floating-point value.IMeans integer.*Indicates floating-point invalid-arithmetic-operand (#IA) exception.

image/svg+xmlProtected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SS segment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SS segment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UD If the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SS segment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made.#UD If the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MF If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.