image/svg+xmlFRSTOR—Restore x87 FPU StateDescriptionLoads the FPU state (operating environment and register stack) from the memory area specified with the source operand. This state data is typically written to the specified memory location by a previous FSAVE/FNSAVE instruc-tion.The FPU operating environment consists of the FPU control word, status word, tag word, instruction pointer, data pointer, and last opcode. Figures 8-9 through 8-12 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, show the layout in memory of the stored environment, depending on the operating mode of the processor (protected or real) and the current operand-size attribute (16-bit or 32-bit). In virtual-8086 mode, the real mode layouts are used. The contents of the FPU register stack are stored in the 80 bytes immediately following the operating environment image.The FRSTOR instruction should be executed in the same operating mode as the corresponding FSAVE/FNSAVE instruction.If one or more unmasked exception bits are set in the new FPU status word, a floating-point exception will be generated upon execution of the next floating-point instruction (except for the no-wait floating-point instructions, see the section titled “Software Exception Handling” in Chapter 8 of the Intel® 64 and IA-32 Architectures Soft-ware Developer’s Manual, Volume 1). To avoid raising exceptions when loading a new operating environment, clear all the exception flags in the FPU status word that is being loaded.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationFPUControlWord := SRC[FPUControlWord];FPUStatusWord := SRC[FPUStatusWord];FPUTagWord := SRC[FPUTagWord];FPUDataPointer := SRC[FPUDataPointer];FPUInstructionPointer := SRC[FPUInstructionPointer];FPULastInstructionOpcode := SRC[FPULastInstructionOpcode];ST(0) := SRC[ST(0)];ST(1) := SRC[ST(1)];ST(2) := SRC[ST(2)];ST(3) := SRC[ST(3)];ST(4) := SRC[ST(4)];ST(5) := SRC[ST(5)];ST(6) := SRC[ST(6)];ST(7) := SRC[ST(7)];FPU Flags AffectedThe C0, C1, C2, C3 flags are loaded.Floating-Point ExceptionsNone; however, if an unmasked exception is loaded in the status word, it is generated upon execution of the next “waiting” floating-point instruction.OpcodeInstruction64-Bit ModeCompat/Leg ModeDescriptionDD /4FRSTOR m94/108byteValidValidLoad FPU state from m94byte or m108byte.

image/svg+xmlProtected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SS segment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SS segment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UD If the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SS segment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made.#UD If the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.