image/svg+xmlFMUL/FMULP/FIMUL—MultiplyDescriptionMultiplies the destination and source operands and stores the product in the destination location. The destination operand is always an FPU data register; the source operand can be an FPU data register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format or in word or doubleword integer format.The no-operand version of the instruction multiplies the contents of the ST(1) register by the contents of the ST(0) register and stores the product in the ST(1) register. The one-operand version multiplies the contents of the ST(0) register by the contents of a memory location (either a floating point or an integer value) and stores the product in the ST(0) register. The two-operand version, multiplies the contents of the ST(0) register by the contents of the ST(i) register, or vice versa, with the result being stored in the register specified with the first operand (the desti-nation operand). The FMULP instructions perform the additional operation of popping the FPU register stack after storing the product. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The no-operand version of the floating-point multiply instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FMUL rather than FMULP.The FIMUL instructions convert an integer source operand to double extended-precision floating-point format before performing the multiplication.The sign of the result is always the exclusive-OR of the source signs, even if one or more of the values being multi-plied is 0 or ∞. When the source operand is an integer 0, it is treated as a +0.The following table shows the results obtained when multiplying various classes of numbers, assuming that neither overflow nor underflow occurs.OpcodeInstruction64-Bit ModeCompat/Leg ModeDescriptionD8 /1FMUL m32fpValidValidMultiply ST(0) by m32fp and store result in ST(0).DC /1FMUL m64fpValidValidMultiply ST(0) by m64fp and store result in ST(0).D8 C8+iFMUL ST(0), ST(i)ValidValidMultiply ST(0) by ST(i) and store result in ST(0).DC C8+iFMUL ST(i), ST(0)ValidValidMultiply ST(i) by ST(0) and store result in ST(i).DE C8+iFMULP ST(i), ST(0)ValidValidMultiply ST(i) by ST(0), store result in ST(i), and pop the register stack.DE C9FMULPValidValidMultiply ST(1) by ST(0), store result in ST(1), and pop the register stack.DA /1FIMUL m32intValidValidMultiply ST(0) by m32int and store result in ST(0).DE /1FIMUL m16intValidValidMultiply ST(0) by m16int and store result in ST(0).

image/svg+xmlThis instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationIF Instruction = FIMULTHENDEST := DEST ∗ ConvertToDoubleExtendedPrecisionFP(SRC);ELSE (* Source operand is floating-point value *)DEST := DEST ∗ SRC;FI;IF Instruction = FMULP THEN PopRegisterStack;FI;FPU Flags AffectedC1Set to 0 if stack underflow occurred.Set if result was rounded up; cleared otherwise.C0, C2, C3 Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IAOperand is an SNaN value or unsupported format.One operand is ±0 and the other is ±∞.#DSource operand is a denormal value.#UResult is too small for destination format.#OResult is too large for destination format.#PValue cannot be represented exactly in destination format.Table 3-29. FMUL/FMULP/FIMUL ResultsDEST− ∞− F− 0+ 0+ F+ ∞NaN− ∞+ ∞+ ∞**− ∞− ∞NaN− F+ ∞+ F+ 0− 0− F− ∞NaN− I+ ∞+ F+ 0− 0− F− ∞NaNSRC− 0*+ 0+ 0− 0− 0*NaN+ 0*− 0− 0+ 0+ 0*NaN+ I− ∞− F− 0+ 0+ F+ ∞NaN+ F− ∞− F− 0+ 0+ F+ ∞NaN+ ∞− ∞− ∞**+ ∞+ ∞NaNNaNNaNNaNNaNNaNNaNNaNNaNNOTES:FMeans finite floating-point value.IMeans Integer.*Indicates invalid-arithmetic-operand (#IA) exception.

image/svg+xmlProtected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SS segment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SS segment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UD If the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SS segment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made.#UD If the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MF If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.