image/svg+xml FILD—Load Integer Description Converts the signed-integer source operand into double extended-precision floating-point format and pushes the value onto the FPU register stack. The source operand can be a word, doubleword, or quadword integer. It is loaded without rounding errors. The sign of the source operand is preserved. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Operation TOP := TOP − 1; ST(0) := ConvertToDoubleExtendedPrecisionFP(SRC); FPU Flags Affected C1Set to 1 if stack overflow occurred; set to 0 otherwise. C0, C2, C3 Undefined. Floating-Point Exceptions #ISStack overflow occurred. Protected Mode Exceptions #GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0)If a memory operand effective address is outside the SS segment limit. #NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code)If a page fault occurs. #AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used. Real-Address Mode Exceptions #GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SSIf a memory operand effective address is outside the SS segment limit. #NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Virtual-8086 Mode Exceptions #GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0)If a memory operand effective address is outside the SS segment limit. #NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code)If a page fault occurs. #AC(0)If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. OpcodeInstruction64-Bit Mode Compat/ Leg Mode Description DF /0FILD m16int ValidValidPush m16int onto the FPU register stack. DB /0FILD m32int ValidValidPush m32int onto the FPU register stack. DF /5FILD m64int ValidValidPush m64int onto the FPU register stack. image/svg+xml Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0)If a memory address referencing the SS segment is in a non-canonical form. #GP(0)If the memory address is in a non-canonical form. #NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code)If a page fault occurs. #AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .