image/svg+xmlFDIVR/FDIVRP/FIDIVR—Reverse DivideDescriptionDivides the source operand by the destination operand and stores the result in the destination location. The desti-nation operand (divisor) is always in an FPU register; the source operand (dividend) can be a register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format, word or doubleword integer format.These instructions perform the reverse operations of the FDIV, FDIVP, and FIDIV instructions. They are provided to support more efficient coding.The no-operand version of the instruction divides the contents of the ST(0) register by the contents of the ST(1) register. The one-operand version divides the contents of a memory location (either a floating-point or an integer value) by the contents of the ST(0) register. The two-operand version, divides the contents of the ST(i) register by the contents of the ST(0) register or vice versa.The FDIVRP instructions perform the additional operation of popping the FPU register stack after storing the result. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The no-operand version of the floating-point divide instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FDIVR rather than FDIVRP.The FIDIVR instructions convert an integer source operand to double extended-precision floating-point format before performing the division.If an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an ∞ of the appropriate sign is stored in the destination operand.The following table shows the results obtained when dividing various classes of numbers, assuming that neither overflow nor underflow occurs.OpcodeInstruction64-Bit ModeCompat/Leg ModeDescriptionD8 /7FDIVR m32fpValidValidDivide m32fp by ST(0) and store result in ST(0).DC /7FDIVR m64fpValidValidDivide m64fp by ST(0) and store result in ST(0).D8 F8+iFDIVR ST(0), ST(i)ValidValidDivide ST(i) by ST(0) and store result in ST(0).DC F0+iFDIVR ST(i), ST(0)ValidValidDivide ST(0) by ST(i) and store result in ST(i).DE F0+iFDIVRP ST(i), ST(0)ValidValidDivide ST(0) by ST(i), store result in ST(i), and pop the register stack.DE F1FDIVRPValidValidDivide ST(0) by ST(1), store result in ST(1), and pop the register stack.DA /7FIDIVR m32intValidValidDivide m32int by ST(0) and store result in ST(0).DE /7FIDIVR m16intValidValidDivide m16int by ST(0) and store result in ST(0).

image/svg+xmlWhen the source operand is an integer 0, it is treated as a +0. This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationIF DEST = 0THEN#Z;ELSEIF Instruction = FIDIVRTHENDEST := ConvertToDoubleExtendedPrecisionFP(SRC) / DEST;ELSE (* Source operand is floating-point value *)DEST := SRC / DEST;FI;FI;IF Instruction = FDIVRP THEN PopRegisterStack;FI;FPU Flags AffectedC1Set to 0 if stack underflow occurred.Set if result was rounded up; cleared otherwise.C0, C2, C3 Undefined.Table 3-25. FDIVR/FDIVRP/FIDIVR ResultsDEST− ∞− F− 0+ 0+ F+ ∞NaN− ∞*+ ∞+ ∞− ∞− ∞*NaNSRC− F+ 0+ F****− F− 0NaN− I+ 0+ F****− F− 0NaN− 0+ 0+ 0**− 0− 0NaN+ 0− 0− 0**+ 0+ 0NaN+ I− 0− F****+ F+ 0NaN+ F− 0− F****+ F+ 0NaN+ ∞*− ∞− ∞+ ∞+ ∞*NaNNaNNaNNaNNaNNaNNaNNaNNaNNOTES:FMeans finite floating-point value.IMeans integer.*Indicates floating-point invalid-arithmetic-operand (#IA) exception.** Indicates floating-point zero-divide (#Z) exception.

image/svg+xmlFloating-Point Exceptions#ISStack underflow occurred.#IAOperand is an SNaN value or unsupported format.±∞ / ±∞; ±0 / ±0#DSource is a denormal value.#ZSRC / ±0, where SRC is not equal to ±0.#UResult is too small for destination format.#OResult is too large for destination format.#PValue cannot be represented exactly in destination format.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SS segment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SS segment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UD If the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SS segment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made.#UD If the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MF If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.