image/svg+xml FCMOV cc —Floating-Point Conditional Move Description Tests the status flags in the EFLAGS register and moves the source operand (second operand) to the destination operand (first operand) if the given test condition is true. The condition for each mnemonic os given in the Descrip- tion column above and in Chapter 8 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 . The source operand is always in the ST(i) register and the destination operand is always ST(0). The FCMOV cc instructions are useful for optimizing small IF constructions. They also help eliminate branching over- head for IF operations and the possibility of branch mispredictions by the processor. A processor may not support the FCMOV cc instructions. Software can check if the FCMOV cc instructions are supported by checking the processor’s feature information with the CPUID instruction (see “COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS” in this chapter). If both the CMOV and FPU feature bits are set, the FCMOV cc instructions are supported. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. IA-32 Architecture Compatibility The FCMOVcc instructions were introduced to the IA-32 Architecture in the P6 family processors and are not avail- able in earlier IA-32 processors. Operation IF condition TRUE THEN ST(0) := ST(i); FI; FPU Flags Affected C1Set to 0 if stack underflow occurred. C0, C2, C3 Undefined. Floating-Point Exceptions #ISStack underflow occurred. Integer Flags Affected None. Opcode*Instruction64-Bit Mode Compat/ Leg Mode* Description DA C0+iFCMOVB ST(0), ST(i)ValidValidMove if below (CF=1). DA C8+iFCMOVE ST(0), ST(i)ValidValidMove if equal (ZF=1). DA D0+iFCMOVBE ST(0), ST(i)ValidValidMove if below or equal (CF=1 or ZF=1). DA D8+iFCMOVU ST(0), ST(i)ValidValidMove if unordered (PF=1). DB C0+iFCMOVNB ST(0), ST(i)ValidValidMove if not below (CF=0). DB C8+iFCMOVNE ST(0), ST(i)ValidValidMove if not equal (ZF=0). DB D0+iFCMOVNBE ST(0), ST(i)ValidValidMove if not below or equal (CF=0 and ZF=0). DB D8+iFCMOVNU ST(0), ST(i)ValidValidMove if not unordered (PF=0). NOTES: *See IA-32 Architecture Compatibility section below. image/svg+xml Protected Mode Exceptions #NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as in protected mode. Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .