image/svg+xml FCHS—Change Sign Description Complements the sign bit of ST(0). This operation changes a positive value into a negative value of equal magni- tude or vice versa. The following table shows the results obtained when changing the sign of various classes of numbers. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Operation SignBit(ST(0)) := NOT (SignBit(ST(0))); FPU Flags Affected C1Set to 0. C0, C2, C3 Undefined. Floating-Point Exceptions #ISStack underflow occurred. Protected Mode Exceptions #NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as in protected mode. Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode. OpcodeInstruction64-Bit Mode Compat/ Leg Mode Description D9 E0FCHSValidValidComplements sign of ST(0). Table 3-20. FCHS Results ST(0) SRCST(0) DEST − ∞ + ∞ − F + F − 0 + 0 + 0 − 0 + F − F + ∞ − ∞ NaNNaN NOTES: *F means finite floating-point value. image/svg+xml 64-Bit Mode Exceptions Same exceptions as in protected mode. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .