image/svg+xml EXTRACTPS—Extract Packed Floating-Point Values Instruction Operand Encoding Description Extracts a single-precision floating-point value from the source operand (second operand) at the 32-bit offset spec- ified from imm8. Immediate bits higher than the most significant offset for the vector length are ignored. The extracted single-precision floating-point value is stored in the low 32-bits of the destination operand In 64-bit mode, destination register operand has default operand size of 64 bits. The upper 32-bits of the register are filled with zero. REX.W is ignored. VEX.128 and EVEX encoded version: When VEX.W1 or EVEX.W1 form is used in 64-bit mode with a general purpose register (GPR) as a destination operand, the packed single quantity is zero extended to 64 bits. VEX.vvvv/EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD. 128-bit Legacy SSE version: When a REX.W prefix is used in 64-bit mode with a general purpose register (GPR) as a destination operand, the packed single quantity is zero extended to 64 bits. The source register is an XMM register. Imm8[1:0] determine the starting DWORD offset from which to extract the 32-bit floating-point value. If VEXTRACTPS is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an #UD exception. Operation VEXTRACTPS (EVEX and VEX.128 encoded version) SRC_OFFSET := IMM8[1:0] IF (64-Bit Mode and DEST is register) DEST[31:0] := (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh DEST[63:32] := 0 ELSE DEST[31:0] := (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh FI Opcode/ Instruction Op / En 64/32 bit Mode Support CPUID Feature Flag Description 66 0F 3A 17 /r ib EXTRACTPS reg/m32, xmm1, imm8 AVVSSE4_1Extract one single-precision floating-point value from xmm1 at the offset specified by imm8 and store the result in reg or m32. Zero extend the results in 64-bit register if applicable. VEX.128.66.0F3A.WIG 17 /r ib VEXTRACTPS reg/m32, xmm1, imm8 AV/VAVXExtract one single-precision floating-point value from xmm1 at the offset specified by imm8 and store the result in reg or m32. Zero extend the results in 64-bit register if applicable. EVEX.128.66.0F3A.WIG 17 /r ib VEXTRACTPS reg/m32, xmm1, imm8 BV/VAVX512FExtract one single-precision floating-point value from xmm1 at the offset specified by imm8 and store the result in reg or m32. Zero extend the results in 64-bit register if applicable. Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4 ANAModRM:r/m (w)ModRM:reg (r)Imm8NA BTuple1 ScalarModRM:r/m (w)ModRM:reg (r)Imm8NA image/svg+xml EXTRACTPS (128-bit Legacy SSE version) SRC_OFFSET := IMM8[1:0] IF (64-Bit Mode and DEST is register) DEST[31:0] := (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh DEST[63:32] := 0 ELSE DEST[31:0] := (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh FI Intel C/C++ Compiler Intrinsic Equivalent EXTRACTPS int _mm_extract_ps (__m128 a, const int nidx); SIMD Floating-Point Exceptions None Other Exceptions VEX-encoded instructions, see Table2-22, “Type 5 Class Exception Conditions”. EVEX-encoded instructions, see Table2-57, “Type E9NF Class Exception Conditions”. Additionally: #UD IF VEX.L = 0. #UDIf VEX.vvvv != 1111B or EVEX.vvvv != 1111B. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .