DIVPS—Divide Packed Single-Precision Floating-Point ValuesInstruction Operand EncodingDescriptionPerforms a SIMD divide of the four, eight or sixteen packed single-precision floating-point values in the first source operand (the second operand) by the four, eight or sixteen packed single-precision floating-point values in the second source operand (the third operand). Results are written to the destination operand (the first operand).EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register. VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed.128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding ZMM register destination are unmodified.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F 5E /rDIVPS xmm1, xmm2/m128AV/VSSEDivide packed single-precision floating-point values in xmm1 by packed single-precision floating-point values in xmm2/mem.VEX.128.0F.WIG 5E /rVDIVPS xmm1, xmm2, xmm3/m128BV/VAVXDivide packed single-precision floating-point values in xmm2 by packed single-precision floating-point values in xmm3/mem.VEX.256.0F.WIG 5E /rVDIVPS ymm1, ymm2, ymm3/m256BV/VAVXDivide packed single-precision floating-point values in ymm2 by packed single-precision floating-point values in ymm3/mem.EVEX.128.0F.W0 5E /rVDIVPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstCV/VAVX512VLAVX512FDivide packed single-precision floating-point values in xmm2 by packed single-precision floating-point values in xmm3/m128/m32bcst and write results to xmm1 subject to writemask k1.EVEX.256.0F.W0 5E /rVDIVPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstCV/VAVX512VLAVX512FDivide packed single-precision floating-point values in ymm2 by packed single-precision floating-point values in ymm3/m256/m32bcst and write results to ymm1 subject to writemask k1.EVEX.512.0F.W0 5E /rVDIVPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}CV/VAVX512FDivide packed single-precision floating-point values in zmm2 by packed single-precision floating-point values in zmm3/m512/m32bcst and write results to zmm1 subject to writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACFullModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA
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