image/svg+xmlCVTTSS2SI—Convert with Truncation Scalar Single-Precision Floating-Point Value to IntegerInstruction Operand EncodingDescriptionConverts a single-precision floating-point value in the source operand (the second operand) to a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand). The source operand can be an XMM register or a 32-bit memory location. The destination operand is a general purpose register. When the source operand is an XMM register, the single-precision floating-point value is contained in the low doubleword of the register. When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid exception is raised. If this exception is masked, the indefinite integer value (80000000H or 80000000_00000000H if operand size is 64 bits) is returned.Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation. See the summary chart at the beginning of this section for encoding data and limits.VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.Software should ensure VCVTTSS2SI is encoded with VEX.L=0. Encoding VCVTTSS2SI with VEX.L=1 may encounter unpredictable behavior across different processor generations.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionF3 0F 2C /rCVTTSS2SI r32, xmm1/m32AV/VSSEConvert one single-precision floating-point value from xmm1/m32 to one signed doubleword integer in r32 using truncation.F3 REX.W 0F 2C /rCVTTSS2SI r64, xmm1/m32AV/N.E.SSEConvert one single-precision floating-point value from xmm1/m32 to one signed quadword integer in r64 using truncation.VEX.LIG.F3.0F.W0 2C /r 1VCVTTSS2SI r32, xmm1/m32NOTES:1. Software should ensure VCVTTSS2SI is encoded with VEX.L=0. Encoding VCVTTSS2SI with VEX.L=1 may encounter unpredictable behavior across different processor generations.AV/VAVXConvert one single-precision floating-point value from xmm1/m32 to one signed doubleword integer in r32 using truncation.VEX.LIG.F3.0F.W1 2C /r 1VCVTTSS2SI r64, xmm1/m32AV/N.E.2AVXConvert one single-precision floating-point value from xmm1/m32 to one signed quadword integer in r64 using truncation.EVEX.LLIG.F3.0F.W0 2C /rVCVTTSS2SI r32, xmm1/m32{sae}BV/VAVX512FConvert one single-precision floating-point value from xmm1/m32 to one signed doubleword integer in r32 using truncation.EVEX.LLIG.F3.0F.W1 2C /rVCVTTSS2SI r64, xmm1/m32{sae}BV/N.E.22. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 ver-sion is used.AVX512FConvert one single-precision floating-point value from xmm1/m32 to one signed quadword integer in r64 using truncation.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (w)ModRM:r/m (r)NANABTuple1 FixedModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlOperation(V)CVTTSS2SI (All versions)IF 64-Bit Mode and OperandSize = 64THENDEST[63:0] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);ELSEDEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);FI;Intel C/C++ Compiler Intrinsic EquivalentVCVTTSS2SI int _mm_cvttss_i32( __m128 a);VCVTTSS2SI int _mm_cvtt_roundss_i32( __m128 a, int sae);VCVTTSS2SI __int64 _mm_cvttss_i64( __m128 a);VCVTTSS2SI __int64 _mm_cvtt_roundss_i64( __m128 a, int sae);CVTTSS2SI int _mm_cvttss_si32( __m128 a);CVTTSS2SI __int64 _mm_cvttss_si64( __m128 a);SIMD Floating-Point ExceptionsInvalid, PrecisionOther ExceptionsSee Table2-20, “Type 3 Class Exception Conditions”; additionally:#UD If VEX.vvvv != 1111B.EVEX-encoded instructions, see Table2-48, “Type E3NF Class Exception Conditions”.

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