CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword IntegersInstruction Operand EncodingDescriptionConverts two, four or eight packed double-precision floating-point values in the source operand (second operand) to two, four or eight packed signed doubleword integers in the destination operand (first operand). When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a YMM/XMM/XMM (low 64 bits) register conditionally updated with writemask k1. The upper bits (MAXVL-1:256) of the corresponding destination are zeroed.VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed.VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:64) of the corresponding ZMM register destination are zeroed.128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are unmodified.Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescription66 0F E6 /rCVTTPD2DQ xmm1, xmm2/m128AV/VSSE2Convert two packed double-precision floating-point values in xmm2/mem to two signed doubleword integers in xmm1 using truncation.VEX.128.66.0F.WIG E6 /rVCVTTPD2DQ xmm1, xmm2/m128AV/VAVXConvert two packed double-precision floating-point values in xmm2/mem to two signed doubleword integers in xmm1 using truncation.VEX.256.66.0F.WIG E6 /rVCVTTPD2DQ xmm1, ymm2/m256AV/VAVXConvert four packed double-precision floating-point values in ymm2/mem to four signed doubleword integers in xmm1 using truncation.EVEX.128.66.0F.W1 E6 /rVCVTTPD2DQ xmm1 {k1}{z}, xmm2/m128/m64bcstBV/VAVX512VLAVX512FConvert two packed double-precision floating-point values in xmm2/m128/m64bcst to two signed doubleword integers in xmm1 using truncation subject to writemask k1.EVEX.256.66.0F.W1 E6 /rVCVTTPD2DQ xmm1 {k1}{z}, ymm2/m256/m64bcstBV/VAVX512VLAVX512FConvert four packed double-precision floating-point values in ymm2/m256/m64bcst to four signed doubleword integers in xmm1 using truncation subject to writemask k1.EVEX.512.66.0F.W1 E6 /rVCVTTPD2DQ ymm1 {k1}{z}, zmm2/m512/m64bcst{sae}BV/VAVX512FConvert eight packed double-precision floating-point values in zmm2/m512/m64bcst to eight signed doubleword integers in ymm1 using truncation subject to writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (w)ModRM:r/m (r)NANABFullModRM:reg (w)ModRM:r/m (r)NANA
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