image/svg+xmlCVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to Doubleword IntegerInstruction Operand EncodingDescriptionConverts a single-precision floating-point value in the source operand (the second operand) to a signed double-word integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand). The source operand can be an XMM register or a memory location. The destination operand is a general-purpose register. When the source operand is an XMM register, the single-precision floating-point value is contained in the low doubleword of the register.When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (2w-1, where w represents the number of bits in the destination format) is returned.Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to produce 64-bit data. See the summary chart at the beginning of this section for encoding data and limits.VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.Software should ensure VCVTSS2SI is encoded with VEX.L=0. Encoding VCVTSS2SI with VEX.L=1 may encounter unpredictable behavior across different processor generations.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionF3 0F 2D /rCVTSS2SI r32, xmm1/m32AV/VSSEConvert one single-precision floating-point value from xmm1/m32 to one signed doubleword integer in r32.F3 REX.W 0F 2D /rCVTSS2SI r64, xmm1/m32AV/N.E.SSEConvert one single-precision floating-point value from xmm1/m32 to one signed quadword integer in r64.VEX.LIG.F3.0F.W0 2D /r 1VCVTSS2SI r32, xmm1/m32NOTES:1. Software should ensure VCVTSS2SI is encoded with VEX.L=0. Encoding VCVTSS2SI with VEX.L=1 may encounter unpredictable behavior across different processor generations.AV/VAVXConvert one single-precision floating-point value from xmm1/m32 to one signed doubleword integer in r32.VEX.LIG.F3.0F.W1 2D /r 1VCVTSS2SI r64, xmm1/m32AV/N.E.2AVXConvert one single-precision floating-point value from xmm1/m32 to one signed quadword integer in r64.EVEX.LLIG.F3.0F.W0 2D /rVCVTSS2SI r32, xmm1/m32{er}BV/VAVX512FConvert one single-precision floating-point value from xmm1/m32 to one signed doubleword integer in r32.EVEX.LLIG.F3.0F.W1 2D /rVCVTSS2SI r64, xmm1/m32{er}BV/N.E.22. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.AVX512FConvert one single-precision floating-point value from xmm1/m32 to one signed quadword integer in r64.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (w)ModRM:r/m (r)NANABTuple1 FixedModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlOperationVCVTSS2SI (EVEX encoded version)IF (SRC *is register*) AND (EVEX.b = 1) THENSET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);ELSE SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);FI;IF 64-bit Mode and OperandSize = 64THENDEST[63:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);ELSEDEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);FI;(V)CVTSS2SI (Legacy and VEX.128 encoded version) IF 64-bit Mode and OperandSize = 64THENDEST[63:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);ELSEDEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);FI;Intel C/C++ Compiler Intrinsic EquivalentVCVTSS2SI int _mm_cvtss_i32( __m128 a);VCVTSS2SI int _mm_cvt_roundss_i32( __m128 a, int r);VCVTSS2SI __int64 _mm_cvtss_i64( __m128 a);VCVTSS2SI __int64 _mm_cvt_roundss_i64( __m128 a, int r);SIMD Floating-Point ExceptionsInvalid, PrecisionOther ExceptionsVEX-encoded instructions, see Table2-20, “Type 3 Class Exception Conditions”; additionally:#UDIf VEX.vvvv != 1111B.EVEX-encoded instructions, see Table2-48, “Type E3NF Class Exception Conditions”.

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