image/svg+xmlCVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point ValueInstruction Operand EncodingDescriptionConverts a single-precision floating-point value in the “convert-from” source operand to a double-precision floating-point value in the destination operand. When the “convert-from” source operand is an XMM register, the single-precision floating-point value is contained in the low doubleword of the register. The result is stored in the low quadword of the destination operand.128-bit Legacy SSE version: The “convert-from” source operand (the second operand) is an XMM register or memory location. Bits (MAXVL-1:64) of the corresponding destination register remain unchanged. The destination operand is an XMM register. VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be an XMM register or a 32-bit memory location. The first source and destination operands are XMM registers. Bits (127:64) of the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.Software should ensure VCVTSS2SD is encoded with VEX.L=0. Encoding VCVTSS2SD with VEX.L=1 may encounter unpredictable behavior across different processor generations.OperationVCVTSS2SD (EVEX encoded version)IF k1[0] or *no writemask*THENDEST[63:0] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC2[31:0]);ELSE IF *merging-masking*; merging-maskingTHEN *DEST[63:0] remains unchanged*ELSE ; zeroing-maskingTHEN DEST[63:0] = 0FI;FI;DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionF3 0F 5A /rCVTSS2SD xmm1, xmm2/m32AV/VSSE2Convert one single-precision floating-point value in xmm2/m32 to one double-precision floating-point value in xmm1.VEX.LIG.F3.0F.WIG 5A /rVCVTSS2SD xmm1, xmm2, xmm3/m32BV/VAVXConvert one single-precision floating-point value in xmm3/m32 to one double-precision floating-point value and merge with high bits of xmm2.EVEX.LLIG.F3.0F.W0 5A /rVCVTSS2SD xmm1 {k1}{z}, xmm2, xmm3/m32{sae}CV/VAVX512FConvert one single-precision floating-point value in xmm3/m32 to one double-precision floating-point value and merge with high bits of xmm2 under writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACTuple1 ScalarModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlVCVTSS2SD (VEX.128 encoded version)DEST[63:0] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC2[31:0])DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0CVTSS2SD (128-bit Legacy SSE version)DEST[63:0] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0]);DEST[MAXVL-1:64] (Unmodified)Intel C/C++ Compiler Intrinsic EquivalentVCVTSS2SD __m128d _mm_cvt_roundss_sd(__m128d a, __m128 b, int r);VCVTSS2SD __m128d _mm_mask_cvt_roundss_sd(__m128d s, __mmask8 m, __m128d a,__m128 b, int r);VCVTSS2SD __m128d _mm_maskz_cvt_roundss_sd(__mmask8 k, __m128d a, __m128 a, int r);VCVTSS2SD __m128d _mm_mask_cvtss_sd(__m128d s, __mmask8 m, __m128d a,__m128 b);VCVTSS2SD __m128d _mm_maskz_cvtss_sd(__mmask8 m, __m128d a,__m128 b);CVTSS2SD __m128d_mm_cvtss_sd(__m128d a, __m128 a);SIMD Floating-Point ExceptionsInvalid, DenormalOther ExceptionsVEX-encoded instructions, see Table2-20, “Type 3 Class Exception Conditions”.EVEX-encoded instructions, see Table2-47, “Type E3 Class Exception Conditions”.

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