image/svg+xmlCVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword IntegersInstruction Operand EncodingDescriptionConverts packed double-precision floating-point values in the source operand (second operand) to packed signed doubleword integers in the destination operand (first operand). When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (2w-1, where w represents the number of bits in the destination format) is returned.EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register condi-tionally updated with writemask k1. The upper bits (MAXVL-1:256/128/64) of the corresponding destination are zeroed.VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed.VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:64) of the corresponding ZMM register destination are zeroed.128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination operand is an XMM register. Bits[127:64] of the destination XMM register are zeroed. However, the upper bits (MAXVL-1:128) of the corresponding ZMM register destination are unmodified. VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.OpcodeInstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionF2 0F E6 /rCVTPD2DQ xmm1, xmm2/m128AV/VSSE2Convert two packed double-precision floating-point values in xmm2/mem to two signed doubleword integers in xmm1.VEX.128.F2.0F.WIG E6 /rVCVTPD2DQ xmm1, xmm2/m128AV/VAVXConvert two packed double-precision floating-point values in xmm2/mem to two signed doubleword integers in xmm1.VEX.256.F2.0F.WIG E6 /rVCVTPD2DQ xmm1, ymm2/m256AV/VAVXConvert four packed double-precision floating-point values in ymm2/mem to four signed doubleword integers in xmm1.EVEX.128.F2.0F.W1 E6 /rVCVTPD2DQ xmm1 {k1}{z}, xmm2/m128/m64bcstBV/VAVX512VLAVX512FConvert two packed double-precision floating-point values in xmm2/m128/m64bcst to two signed doubleword integers in xmm1 subject to writemask k1.EVEX.256.F2.0F.W1 E6 /rVCVTPD2DQ xmm1 {k1}{z}, ymm2/m256/m64bcstBV/VAVX512VLAVX512FConvert four packed double-precision floating-point values in ymm2/m256/m64bcst to four signed doubleword integers in xmm1 subject to writemask k1.EVEX.512.F2.0F.W1 E6 /rVCVTPD2DQ ymm1 {k1}{z}, zmm2/m512/m64bcst{er}BV/VAVX512FConvert eight packed double-precision floating-point values in zmm2/m512/m64bcst to eight signed doubleword integers in ymm1 subject to writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (w)ModRM:r/m (r)NANABFullModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlOperationVCVTPD2DQ (EVEX encoded versions) when src operand is a register(KL, VL) = (2, 128), (4, 256), (8, 512)IF (VL = 512) AND (EVEX.b = 1) THENSET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);ELSE SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);FI;FOR j := 0 TO KL-1i := j * 32k := j * 64IF k1[j] OR *no writemask*THEN DEST[i+31:i] :=Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k])ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+31:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL/2] := 0Figure 3-12. VCVTPD2DQ (VEX.256 encoded version)DESTSRCX0X1X2X3X3X2X1X00

image/svg+xmlVCVTPD2DQ (EVEX encoded versions) when src operand is a memory source(KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 32k := j * 64IF k1[j] OR *no writemask*THEN IF (EVEX.b = 1) THENDEST[i+31:i] :=Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])ELSE DEST[i+31:i] :=Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k])FI;ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+31:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL/2] := 0VCVTPD2DQ (VEX.256 encoded version)DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])DEST[95:64] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[191:128])DEST[127:96] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[255:192)DEST[MAXVL-1:128] := 0VCVTPD2DQ (VEX.128 encoded version)DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])DEST[MAXVL-1:64] := 0CVTPD2DQ (128-bit Legacy SSE version)DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])DEST[127:64] := 0DEST[MAXVL-1:128] (unmodified)

image/svg+xmlIntel C/C++ Compiler Intrinsic EquivalentVCVTPD2DQ __m256i _mm512_cvtpd_epi32( __m512d a);VCVTPD2DQ __m256i _mm512_mask_cvtpd_epi32( __m256i s, __mmask8 k, __m512d a);VCVTPD2DQ __m256i _mm512_maskz_cvtpd_epi32( __mmask8 k, __m512d a);VCVTPD2DQ __m256i _mm512_cvt_roundpd_epi32( __m512d a, int r);VCVTPD2DQ __m256i _mm512_mask_cvt_roundpd_epi32( __m256i s, __mmask8 k, __m512d a, int r);VCVTPD2DQ __m256i _mm512_maskz_cvt_roundpd_epi32( __mmask8 k, __m512d a, int r);VCVTPD2DQ __m128i _mm256_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m256d a);VCVTPD2DQ __m128i _mm256_maskz_cvtpd_epi32( __mmask8 k, __m256d a);VCVTPD2DQ __m128i _mm_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m128d a);VCVTPD2DQ __m128i _mm_maskz_cvtpd_epi32( __mmask8 k, __m128d a);VCVTPD2DQ __m128i _mm256_cvtpd_epi32 (__m256d src)CVTPD2DQ __m128i _mm_cvtpd_epi32 (__m128d src)SIMD Floating-Point ExceptionsInvalid, PrecisionOther ExceptionsSee Table2-19, “Type 2 Class Exception Conditions”.EVEX-encoded instructions, see Table2-46, “Type E2 Class Exception Conditions”.Additionally:#UDIf VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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