CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point ValuesInstruction Operand EncodingDescriptionConverts four, eight or sixteen packed signed doubleword integers in the source operand to four, eight or sixteen packed single-precision floating-point values in the destination operand.EVEX encoded versions: The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination operand is a YMM register. Bits (MAXVL-1:256) of the corresponding register destination are zeroed.VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding register destination are zeroed.128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination operand is an XMM register. The upper Bits (MAXVL-1:128) of the corresponding register destination are unmodi-fied.VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.OpcodeInstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F 5B /rCVTDQ2PS xmm1, xmm2/m128AV/VSSE2Convert four packed signed doubleword integers from xmm2/mem to four packed single-precision floating-point values in xmm1.VEX.128.0F.WIG 5B /rVCVTDQ2PS xmm1, xmm2/m128AV/VAVXConvert four packed signed doubleword integers from xmm2/mem to four packed single-precision floating-point values in xmm1.VEX.256.0F.WIG 5B /rVCVTDQ2PS ymm1, ymm2/m256AV/VAVXConvert eight packed signed doubleword integers from ymm2/mem to eight packed single-precision floating-point values in ymm1.EVEX.128.0F.W0 5B /rVCVTDQ2PS xmm1 {k1}{z}, xmm2/m128/m32bcstBV/VAVX512VLAVX512FConvert four packed signed doubleword integers from xmm2/m128/m32bcst to four packed single-precision floating-point values in xmm1with writemask k1.EVEX.256.0F.W0 5B /rVCVTDQ2PS ymm1 {k1}{z}, ymm2/m256/m32bcstBV/VAVX512VLAVX512FConvert eight packed signed doubleword integers from ymm2/m256/m32bcst to eight packed single-precision floating-point values in ymm1with writemask k1.EVEX.512.0F.W0 5B /rVCVTDQ2PS zmm1 {k1}{z}, zmm2/m512/m32bcst{er}BV/VAVX512FConvert sixteen packed signed doubleword integers from zmm2/m512/m32bcst to sixteen packed single-precision floating-point values in zmm1with writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (w)ModRM:r/m (r)NANABFullModRM:reg (w)ModRM:r/m (r)NANA
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