image/svg+xmlCVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point ValuesInstruction Operand EncodingDescriptionConverts four, eight or sixteen packed signed doubleword integers in the source operand to four, eight or sixteen packed single-precision floating-point values in the destination operand.EVEX encoded versions: The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination operand is a YMM register. Bits (MAXVL-1:256) of the corresponding register destination are zeroed.VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding register destination are zeroed.128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination operand is an XMM register. The upper Bits (MAXVL-1:128) of the corresponding register destination are unmodi-fied.VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.OpcodeInstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F 5B /rCVTDQ2PS xmm1, xmm2/m128AV/VSSE2Convert four packed signed doubleword integers from xmm2/mem to four packed single-precision floating-point values in xmm1.VEX.128.0F.WIG 5B /rVCVTDQ2PS xmm1, xmm2/m128AV/VAVXConvert four packed signed doubleword integers from xmm2/mem to four packed single-precision floating-point values in xmm1.VEX.256.0F.WIG 5B /rVCVTDQ2PS ymm1, ymm2/m256AV/VAVXConvert eight packed signed doubleword integers from ymm2/mem to eight packed single-precision floating-point values in ymm1.EVEX.128.0F.W0 5B /rVCVTDQ2PS xmm1 {k1}{z}, xmm2/m128/m32bcstBV/VAVX512VLAVX512FConvert four packed signed doubleword integers from xmm2/m128/m32bcst to four packed single-precision floating-point values in xmm1with writemask k1.EVEX.256.0F.W0 5B /rVCVTDQ2PS ymm1 {k1}{z}, ymm2/m256/m32bcstBV/VAVX512VLAVX512FConvert eight packed signed doubleword integers from ymm2/m256/m32bcst to eight packed single-precision floating-point values in ymm1with writemask k1.EVEX.512.0F.W0 5B /rVCVTDQ2PS zmm1 {k1}{z}, zmm2/m512/m32bcst{er}BV/VAVX512FConvert sixteen packed signed doubleword integers from zmm2/m512/m32bcst to sixteen packed single-precision floating-point values in zmm1with writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (w)ModRM:r/m (r)NANABFullModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlOperationVCVTDQ2PS (EVEX encoded versions) when SRC operand is a register(KL, VL) = (4, 128), (8, 256), (16, 512)IF (VL = 512) AND (EVEX.b = 1) THENSET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC); ; refer to Table 15-4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1ELSE SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC); ; refer to Table 15-4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1FI;FOR j := 0 TO KL-1i := j * 32IF k1[j] OR *no writemask*THEN DEST[i+31:i] :=Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+31:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0VCVTDQ2PS (EVEX encoded versions) when SRC operand is a memory source(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 32IF k1[j] OR *no writemask*THEN IF (EVEX.b = 1) THENDEST[i+31:i] :=Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])ELSE DEST[i+31:i] :=Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])FI;ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+31:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0

image/svg+xmlVCVTDQ2PS (VEX.256 encoded version)DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])DEST[63:32] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])DEST[95:64] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])DEST[127:96] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[127:96)DEST[159:128] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[159:128])DEST[191:160] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[191:160])DEST[223:192] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[223:192])DEST[255:224] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[255:224)DEST[MAXVL-1:256] := 0VCVTDQ2PS (VEX.128 encoded version)DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])DEST[63:32] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])DEST[95:64] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])DEST[127:96] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)DEST[MAXVL-1:128] := 0CVTDQ2PS (128-bit Legacy SSE version)DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])DEST[63:32] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])DEST[95:64] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])DEST[127:96] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)DEST[MAXVL-1:128] (unmodified)Intel C/C++ Compiler Intrinsic EquivalentVCVTDQ2PS __m512 _mm512_cvtepi32_ps( __m512i a);VCVTDQ2PS __m512 _mm512_mask_cvtepi32_ps( __m512 s, __mmask16 k, __m512i a);VCVTDQ2PS __m512 _mm512_maskz_cvtepi32_ps( __mmask16 k, __m512i a);VCVTDQ2PS __m512 _mm512_cvt_roundepi32_ps( __m512i a, int r);VCVTDQ2PS __m512 _mm512_mask_cvt_roundepi_ps( __m512 s, __mmask16 k, __m512i a, int r);VCVTDQ2PS __m512 _mm512_maskz_cvt_roundepi32_ps( __mmask16 k, __m512i a, int r);VCVTDQ2PS __m256 _mm256_mask_cvtepi32_ps( __m256 s, __mmask8 k, __m256i a);VCVTDQ2PS __m256 _mm256_maskz_cvtepi32_ps( __mmask8 k, __m256i a);VCVTDQ2PS __m128 _mm_mask_cvtepi32_ps( __m128 s, __mmask8 k, __m128i a);VCVTDQ2PS __m128 _mm_maskz_cvtepi32_ps( __mmask8 k, __m128i a);CVTDQ2PS __m256 _mm256_cvtepi32_ps (__m256i src)CVTDQ2PS __m128 _mm_cvtepi32_ps (__m128i src)SIMD Floating-Point ExceptionsPrecisionOther ExceptionsVEX-encoded instructions, see Table2-19, “Type 2 Class Exception Conditions”. EVEX-encoded instructions, see Table2-46, “Type E2 Class Exception Conditions”.Additionally:#UDIf VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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