CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point ValuesInstruction Operand EncodingDescriptionConverts two, four or eight packed signed doubleword integers in the source operand (the second operand) to two, four or eight packed double-precision floating-point values in the destination operand (the first operand). EVEX encoded versions: The source operand can be a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit memory location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1. Attempt to encode this instruction with EVEX embedded rounding is ignored.VEX.256 encoded version: The source operand is an XMM register or 128- bit memory location. The destination operand is a YMM register. VEX.128 encoded version: The source operand is an XMM register or 64- bit memory location. The destination operand is a XMM register. The upper Bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed.128-bit Legacy SSE version: The source operand is an XMM register or 64- bit memory location. The destination operand is an XMM register. The upper Bits (MAXVL-1:128) of the corresponding ZMM register destination are unmodified.VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionF3 0F E6 /rCVTDQ2PD xmm1, xmm2/m64AV/VSSE2Convert two packed signed doubleword integers from xmm2/mem to two packed double-precision floating-point values in xmm1.VEX.128.F3.0F.WIG E6 /rVCVTDQ2PD xmm1, xmm2/m64AV/VAVXConvert two packed signed doubleword integers from xmm2/mem to two packed double-precision floating-point values in xmm1.VEX.256.F3.0F.WIG E6 /rVCVTDQ2PD ymm1, xmm2/m128AV/VAVXConvert four packed signed doubleword integers from xmm2/mem to four packed double-precision floating-point values in ymm1.EVEX.128.F3.0F.W0 E6 /rVCVTDQ2PD xmm1 {k1}{z}, xmm2/m64/m32bcst BV/VAVX512VLAVX512FConvert 2 packed signed doubleword integers from xmm2/m64/m32bcst to eight packed double-precision floating-point values in xmm1 with writemask k1.EVEX.256.F3.0F.W0 E6 /rVCVTDQ2PD ymm1 {k1}{z}, xmm2/m128/m32bcst BV/VAVX512VLAVX512FConvert 4 packed signed doubleword integers from xmm2/m128/m32bcst to 4 packed double-precision floating-point values in ymm1 with writemask k1.EVEX.512.F3.0F.W0 E6 /rVCVTDQ2PD zmm1 {k1}{z}, ymm2/m256/m32bcst BV/VAVX512FConvert eight packed signed doubleword integers from ymm2/m256/m32bcst to eight packed double-precision floating-point values in zmm1 with writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (w)ModRM:r/m (r)NANABHalfModRM:reg (w)ModRM:r/m (r)NANA
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