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CPUID—CPU Identification
Instruction Operand Encoding
Description
The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction. If a software procedure can
set and clear this flag, the processor executing the procedure supports the CPUID instruction. This instruction oper-
ates the same in non-64-bit modes and 64-bit mode.
CPUID returns processor identification and feature information in the EAX, EBX, ECX, and EDX registers.
1
The
instruction’s output is dependent on the contents of the EAX register upon execution (in some cases, ECX as well).
For example, the following pseudocode loads EAX with 00H and causes CPUID to return a Maximum Return Value
and the Vendor Identification String in the appropriate registers:
MOV EAX, 00H
CPUID
Table 3-8 shows information returned, depending on the initial value loaded into the EAX register.
Two types of information are returned: basic and extended function information. If a value entered for CPUID.EAX
is higher than the maximum input value for basic or extended function for that processor then the data for the
highest basic information leaf is returned. For example, using some Intel processors, the following is true:
CPUID.EAX = 05H (* Returns MONITOR/MWAIT leaf. *)
CPUID.EAX = 0AH (* Returns Architectural Performance Monitoring leaf. *)
CPUID.EAX = 0BH (* Returns Extended Topology Enumeration leaf. *)
2
CPUID.EAX =1FH (* Returns V2 Extended Topology Enumeration leaf. *)
2
CPUID.EAX = 80000008H (* Returns linear/physical address size data. *)
CPUID.EAX = 8000000AH (* INVALID: Returns same information as CPUID.EAX = 0BH. *)
If a value entered for CPUID.EAX is less than or equal to the maximum input value and the leaf is not supported on
that processor then 0 is returned in all the registers.
When CPUID returns the highest basic leaf information as a result of an invalid input EAX value, any dependence
on input ECX value in the basic leaf is honored.
CPUID can be executed at any privilege level to serialize instruction execution. Serializing instruction execution
guarantees that any modifications to flags, registers, and memory for previous instructions are completed before
the next instruction is fetched and executed.
See also:
“Serializing Instructions” in Chapter 8, “Multiple-Processor Management,” in the
Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3A
.
“Caching Translation Information” in Chapter 4, “Paging,” in the
Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 3A
.
OpcodeInstructionOp/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F A2CPUIDZOValidValidReturns processor identification and feature
information to the EAX, EBX, ECX, and EDX
registers, as determined by input entered in
EAX (in some cases, ECX as well).
Op/EnOperand 1Operand 2Operand 3Operand 4
ZONANANANA
1.On Intel 64 processors, CPUID clears the high 32 bits of the RAX/RBX/RCX/RDX registers in all modes.
2.CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking for the existence of CPUID leaf 1FH before using
leaf 0BH.
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Table 3-8. Information Returned by CPUID Instruction
Initial EAX
ValueInformation Provided about the Processor
Basic CPUID Information
0HEAXMaximum Input Value for Basic CPUID Information.
EBX“Genu”
ECX“ntel”
EDX“ineI”
01HEAXVersion Information: Type, Family, Model, and Stepping ID (see Figure3-6).
EBXBits 07 - 00: Brand Index.
Bits 15 - 08: CLFLUSH line size (Value
∗
8
=
cache line size in bytes; used also by CLFLUSHOPT).
Bits 23 - 16: Maximum number of addressable IDs for logical processors in this physical package*.
Bits 31 - 24: Initial APIC ID**.
ECXFeature Information (see Figure3-7 and Table 3-10).
EDXFeature Information (see Figure3-8 and Table 3-11).
NOTES:
*The nearest power-of-2 integer that is not smaller than EBX[23:16] is the number of unique initial APIC
IDs reserved for addressing different logical processors in a physical package. This field is only valid if
CPUID.1.EDX.HTT[bit 28]= 1.
**
The 8-bit initial APIC ID in EBX[31:24] is replaced by the 32-bit x2APIC ID, available in Leaf 0BH and
Leaf 1FH.
02HEAXCache and TLB Information (see Table 3-12).
EBXCache and TLB Information.
ECXCache and TLB Information.
EDXCache and TLB Information.
03HEAXReserved.
EBXReserved.
ECXBits 00 - 31 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the
value in this register is reserved.)
EDXBits 32 - 63 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the
value in this register is reserved.)
NOTES:
Processor serial number (PSN) is not supported in the Pentium 4 processor or later. On all models, use
the PSN flag (returned using CPUID) to check for PSN support before accessing the feature.
CPUID leaves above 2 and below 80000000H are visible only when IA32_MISC_ENABLE[bit 22] has its default value of 0.
Deterministic Cache Parameters Leaf
04H
NOTES:
Leaf 04H output depends on the initial value in ECX.*
See also: “INPUT EAX = 04H: Returns Deterministic Cache Parameters for Each Level” on page245.
EAXBits 04 - 00: Cache Type Field.
0 = Null - No more caches.
1 = Data Cache.
2 = Instruction Cache.
3 = Unified Cache.
4-31 = Reserved.
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Bits 07 - 05: Cache Level (starts at 1).
Bit 08: Self Initializing cache level (does not need SW initialization).
Bit 09: Fully Associative cache.
Bits 13 - 10: Reserved.
Bits 25 - 14: Maximum number of addressable IDs for logical processors sharing this cache**,***.
Bits 31 - 26: Maximum number of addressable IDs for processor cores in the physical
package**,****,*****.
EBXBits 11 - 00: L = System Coherency Line Size**.
Bits 21 - 12: P = Physical Line partitions**.
Bits 31 - 22: W = Ways of associativity**.
ECXBits 31-00: S = Number of Sets**.
EDXBit 00: Write-Back Invalidate/Invalidate.
0=WBINVD/INVD from threads sharing this cache acts upon lower level caches for threads sharing this
cache.
1=WBINVD/INVD is not guaranteed to act upon lower level caches of non-originating threads sharing
this cache.
Bit 01: Cache Inclusiveness.
0=Cache is not inclusive of lower cache levels.
1=Cache is inclusive of lower cache levels.
Bit 02: Complex Cache Indexing.
0=Direct mapped cache.
1=A complex function is used to index the cache, potentially using all address bits.
Bits 31 - 03: Reserved = 0.
NOTES:
* If ECX contains an invalid sub leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n+1 is invalid if sub-
leaf n returns EAX[4:0] as 0.
**Add one to the return value to get the result.
***The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14]) is the number of unique ini-
tial APIC IDs reserved for addressing different logical processors sharing this cache.
**** The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26]) is the number of unique
Core_IDs reserved for addressing different processor cores in a physical package. Core ID is a subset of
bits of the initial APIC ID.
***** The returned value is constant for valid initial values in ECX. Valid ECX values start from 0.
MONITOR/MWAIT Leaf
05HEAXBits 15 - 00: Smallest monitor-line size in bytes (default is processor's monitor granularity).
Bits 31 - 16: Reserved = 0.
EBXBits 15 - 00: Largest monitor-line size in bytes (default is processor's monitor granularity).
Bits 31 - 16: Reserved = 0.
ECXBit 00: Enumeration of Monitor-Mwait extensions (beyond EAX and EBX registers) supported.
Bit 01: Supports treating interrupts as break-event for MWAIT, even when interrupts disabled.
Bits 31 - 02: Reserved.
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
ValueInformation Provided about the Processor
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EDXBits 03 - 00: Number of C0* sub C-states supported using MWAIT.
Bits 07 - 04: Number of C1* sub C-states supported using MWAIT.
Bits 11 - 08: Number of C2* sub C-states supported using MWAIT.
Bits 15 - 12: Number of C3* sub C-states supported using MWAIT.
Bits 19 - 16: Number of C4* sub C-states supported using MWAIT.
Bits 23 - 20: Number of C5* sub C-states supported using MWAIT.
Bits 27 - 24: Number of C6* sub C-states supported using MWAIT.
Bits 31 - 28: Number of C7* sub C-states supported using MWAIT.
NOTE:
* The definition of C0 through C7 states for MWAIT extension are processor-specific C-states, not ACPI C-
states.
Thermal and Power Management Leaf
06HEAXBit 00: Digital temperature sensor is supported if set.
Bit 01: Intel Turbo Boost Technology available (see description of IA32_MISC_ENABLE[38]).
Bit 02: ARAT. APIC-Timer-always-running feature is supported if set.
Bit 03: Reserved.
Bit 04: PLN. Power limit notification controls are supported if set.
Bit 05: ECMD. Clock modulation duty cycle extension is supported if set.
Bit 06: PTM. Package thermal management is supported if set.
Bit 07: HWP. HWP base registers (IA32_PM_ENABLE[bit 0], IA32_HWP_CAPABILITIES,
IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
Bit 08: HWP_Notification. IA32_HWP_INTERRUPT MSR is supported if set.
Bit 09: HWP_Activity_Window. IA32_HWP_REQUEST[bits 41:32] is supported if set.
Bit 10: HWP_Energy_Performance_Preference. IA32_HWP_REQUEST[bits 31:24] is supported if set.
Bit 11: HWP_Package_Level_Request. IA32_HWP_REQUEST_PKG MSR is supported if set.
Bit 12: Reserved.
Bit 13: HDC. HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, IA32_THREAD_STALL MSRs are
supported if set.
Bit 14: Intel® Turbo Boost Max Technology 3.0 available.
Bit 15: HWP Capabilities. Highest Performance change is supported if set.
Bit 16: HWP PECI override is supported if set.
Bit 17: Flexible HWP is supported if set.
Bit 18: Fast access mode for the IA32_HWP_REQUEST MSR is supported if set.
Bit 19: HW_FEEDBACK. IA32_HW_FEEDBACK_PTR MSR, IA32_HW_FEEDBACK_CONFIG MSR,
IA32_PACKAGE_THERM_STATUS MSR bit 26, and IA32_PACKAGE_THERM_INTERRUPT MSR bit 25 are
supported if set.
Bit 20: Ignoring Idle Logical Processor HWP request is supported if set.
Bits 22 - 21: Reserved.
Bit 23: Intel® Thread Director supported if set. IA32_HW_FEEDBACK_CHAR and
IA32_HW_FEEDBACK_THREAD_CONFIG MSRs are supported if set.
Bits 31 - 24: Reserved.
EBXBits 03 - 00: Number of Interrupt Thresholds in Digital Thermal Sensor.
Bits 31 - 04: Reserved.
ECXBit 00: Hardware Coordination Feedback Capability (Presence of IA32_MPERF and IA32_APERF). The
capability to provide a measure of delivered processor performance (since last reset of the counters), as
a percentage of the expected processor performance when running at the TSC frequency.
Bits 02 - 01: Reserved = 0.
Bit 03: The processor supports performance-energy bias preference if CPUID.06H:ECX.SETBH[bit 3] is set
and it also implies the presence of a new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H).
Bits 07 - 04: Reserved = 0.
Bits 15 - 08: Number of Intel® Thread Director classes supported by the processor. Information for that
many classes is written into the Intel Thread Director Table by the hardware.
Bits 31 - 16: Reserved = 0.
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
ValueInformation Provided about the Processor
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EDXBits 7-0: Bitmap of supported hardware feedback interface capabilities.
0 = When set to 1, indicates support for performance capability reporting.
1 = When set to 1, indicates support for energy efficiency capability reporting.
2-7 = Reserved
Bits 11-8: Enumerates the size of the hardware feedback interface structure in number of 4 KB pages;
add one to the return value to get the result.
Bits 31-16: Index (starting at 0) of this logical processor's row in the hardware feedback interface struc-
ture. Note that on some parts the index may be same for multiple logical processors. On some parts the
indices may not be contiguous, i.e., there may be unused rows in the hardware feedback interface struc-
ture.
NOTE:
Bits 0 and 1 will always be set together.
Structured Extended Feature Flags Enumeration Leaf (Output depends on ECX input value)
07HSub-leaf 0 (Input ECX = 0). *
EAXBits 31 - 00: Reports the maximum input value for supported leaf 7 sub-leaves.
EBXBit 00: FSGSBASE. Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
Bit 01: IA32_TSC_ADJUST MSR is supported if 1.
Bit 02: SGX. Supports Intel® Software Guard Extensions (Intel® SGX Extensions) if 1.
Bit 03: BMI1.
Bit 04: HLE.
Bit 05: AVX2.
Bit 06: FDP_EXCPTN_ONLY. x87 FPU Data Pointer updated only on x87 exceptions if 1.
Bit 07: SMEP. Supports Supervisor-Mode Execution Prevention if 1.
Bit 08: BMI2.
Bit 09: Supports Enhanced REP MOVSB/STOSB if 1.
Bit 10: INVPCID. If 1, supports INVPCID instruction for system software that manages process-context
identifiers.
Bit 11: RTM.
Bit 12: RDT-M. Supports Intel® Resource Director Technology (Intel® RDT) Monitoring capability if 1.
Bit 13: Deprecates FPU CS and FPU DS values if 1.
Bit 14: MPX. Supports Intel® Memory Protection Extensions if 1.
Bit 15: RDT-A. Supports Intel® Resource Director Technology (Intel® RDT) Allocation capability if 1.
Bit 16: AVX512F.
Bit 17: AVX512DQ.
Bit 18: RDSEED.
Bit 19: ADX.
Bit 20: SMAP. Supports Supervisor-Mode Access Prevention (and the CLAC/STAC instructions) if 1.
Bit 21: AVX512_IFMA.
Bit 22: Reserved.
Bit 23: CLFLUSHOPT.
Bit 24: CLWB.
Bit 25: Intel Processor Trace.
Bit 26: AVX512PF. (Intel® Xeon Phi™ only.)
Bit 27: AVX512ER. (Intel® Xeon Phi™ only.)
Bit 28: AVX512CD.
Bit 29: SHA. supports Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions) if 1.
Bit 30: AVX512BW.
Bit 31: AVX512VL.
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
ValueInformation Provided about the Processor
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ECXBit 00: PREFETCHWT1. (Intel® Xeon Phi™ only.)
Bit 01: AVX512_VBMI.
Bit 02: UMIP. Supports user-mode instruction prevention if 1.
Bit 03: PKU. Supports protection keys for user-mode pages if 1.
Bit 04: OSPKE. If 1, OS has set CR4.PKE to enable protection keys (and the RDPKRU/WRPKRU instruc-
tions).
Bit 05: WAITPKG.
Bit 06: AVX512_VBMI2.
Bit 07: CET_SS. Supports CET shadow stack features if 1. Processors that set this bit define bits 1:0 of the
IA32_U_CET and IA32_S_CET MSRs. Enumerates support for the following MSRs:
IA32_INTERRUPT_SPP_TABLE_ADDR, IA32_PL3_SSP, IA32_PL2_SSP, IA32_PL1_SSP, and
IA32_PL0_SSP.
Bit 08: GFNI.
Bit 09: VAES.
Bit 10: VPCLMULQDQ.
Bit 11: AVX512_VNNI.
Bit 12: AVX512_BITALG.
Bits 13: TME_EN. If 1, the following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE,
IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE.
Bit 14: AVX512_VPOPCNTDQ.
Bit 15: Reserved.
Bit 16: LA57. Supports 57-bit linear addresses and five-level paging if 1.
Bits 21 - 17: The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode.
Bit 22: RDPID and IA32_TSC_AUX are available if 1.
Bit 23: KL. Supports Key Locker if 1.
Bit 24: Reserved.
Bit 25: CLDEMOTE. Supports cache line demote if 1.
Bit 26: Reserved.
Bit 27: MOVDIRI. Supports MOVDIRI if 1.
Bit 28: MOVDIR64B. Supports MOVDIR64B if 1.
Bit 29: Reserved.
Bit 30: SGX_LC. Supports SGX Launch Configuration if 1.
Bit 31: PKS. Supports protection keys for supervisor-mode pages if 1.
EDXBit 01: Reserved.
Bit 02: AVX512_4VNNIW. (Intel® Xeon Phi™ only.)
Bit 03: AVX512_4FMAPS. (Intel® Xeon Phi™ only.)
Bit 04: Fast Short REP MOV.
Bits 07-05: Reserved.
Bit 08: AVX512_VP2INTERSECT.
Bit 09: Reserved.
Bit 10: MD_CLEAR supported.
Bits 13-11: Reserved.
Bit 14: SERIALIZE.
Bit 15: Hybrid. If 1, the processor is identified as a hybrid part.
Bits 17-16: Reserved.
Bit 18: PCONFIG. Supports PCONFIG if 1.
Bit 19: Reserved.
Bit 20: CET_IBT. Supports CET indirect branch tracking features if 1. Processors that set this bit define
bits 5:2 and bits 63:10 of the IA32_U_CET and IA32_S_CET MSRs.
Bits 25 - 21: Reserved.
Bit 26: Enumerates support for indirect branch restricted speculation (IBRS) and the indirect branch pre-
dictor barrier (IBPB). Processors that set this bit support the IA32_SPEC_CTRL MSR and the
IA32_PRED_CMD MSR. They allow software to set IA32_SPEC_CTRL[0] (IBRS) and IA32_PRED_CMD[0]
(IBPB).
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
ValueInformation Provided about the Processor
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Bit 27: Enumerates support for single thread indirect branch predictors (STIBP). Processors that set this
bit support the IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[1] (STIBP).
Bit 28: Enumerates support for L1D_FLUSH. Processors that set this bit support the IA32_FLUSH_CMD
MSR. They allow software to set IA32_FLUSH_CMD[0] (L1D_FLUSH).
Bit 29: Enumerates support for the IA32_ARCH_CAPABILITIES MSR.
Bit 30: Enumerates support for the IA32_CORE_CAPABILITIES MSR.
IA32_CORE_CAPABILITIES is an architectural MSR that enumerates model-specific features. A bit being
set in this MSR indicates that a model specific feature is supported; software must still consult CPUID
family/model/stepping to determine the behavior of the enumerated feature as features enumerated in
IA32_CORE_CAPABILITIES may have different behavior on different processor models.
Additionally, on hybrid parts (CPUID.07H.0H:EDX[15]=1), software must consult the native model ID and
core type from the Hybrid Information Enumeration Leaf.
Bit 31: Enumerates support for Speculative Store Bypass Disable (SSBD). Processors that set this bit sup-
port the IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[2] (SSBD).
NOTE:
* If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n
exceeds the value that sub-leaf 0 returns in EAX.
Structured Extended Feature Enumeration Sub-leaf (EAX = 07H, ECX = 1)
07H
NOTES:
Leaf 07H output depends on the initial value in ECX.
If ECX contains an invalid sub leaf index, EAX/EBX/ECX/EDX return 0.
EAX
This field reports 0 if the sub-leaf index,
1
, is invalid.
Bits 03-00: Reserved.
Bit 04: AVX-VNNI. AVX (VEX-encoded) versions of the Vector Neural Network Instructions.
Bit 05: AVX512_BF16. Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion
instructions from IEEE single precision.
Bits 09-06: Reserved.
Bit 10: If 1, supports fast zero-length REP MOVSB.
Bit 11: If 1, supports fast short REP STOSB.
Bit 12: If 1, supports fast short REP CMPSB, REP SCASB.
Bits 21-13: Reserved.
Bit 22: HRESET. If 1, supports history reset via the HRESET instruction and the IA32_HRESET_ENABLE
MSR. When set, indicates that the Processor History Reset Leaf (EAX = 20H) is valid.
Bits 31-23: Reserved.
EBX
This field reports 0 if the sub-leaf index,
1
, is invalid.
Bit 00: Enumerates the presence of the IA32_PPIN and IA32_PPIN_CTL MSRs. If 1, these MSRs are sup-
ported.
Bits 31-01: Reserved.
ECXThis field reports 0 if the sub-leaf index,
1
, is invalid; otherwise it is reserved.
EDXThis field reports 0 if the sub-leaf index,
1
, is invalid; otherwise it is reserved.
Direct Cache Access Information Leaf
09HEAXValue of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).
EBXReserved.
ECXReserved.
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
ValueInformation Provided about the Processor
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EDXReserved.
Architectural Performance Monitoring Leaf
0AHEAXBits 07 - 00: Version ID of architectural performance monitoring.
Bits 15 - 08: Number of general-purpose performance monitoring counter per logical processor.
Bits 23 - 16: Bit width of general-purpose, performance monitoring counter.
Bits 31 - 24: Length of EBX bit vector to enumerate architectural performance monitoring events. Archi-
tectural event x is supported if EBX[x]=0 && EAX[31:24]>x.
EBXBit 00: Core cycle event not available if 1 or if EAX[31:24]<1.
Bit 01: Instruction retired event not available if 1 or if EAX[31:24]<2.
Bit 02: Reference cycles event not available if 1 or if EAX[31:24]<3.
Bit 03: Last-level cache reference event not available if 1 or if EAX[31:24]<4.
Bit 04: Last-level cache misses event not available if 1 or if EAX[31:24]<5.
Bit 05: Branch instruction retired event not available if 1 or if EAX[31:24]<6.
Bit 06: Branch mispredict retired event not available if 1 or if EAX[31:24]<7.
Bit 07: Top-down slots event not available if 1 or if EAX[31:24]<8.
Bits 31 - 08: Reserved = 0.
ECXBits 31 - 00: Supported fixed counters bit mask. Fixed-function performance counter 'i' is supported if bit
‘i’ is 1 (first counter index starts at zero). It is recommended to use the following logic to determine if a
Fixed Counter is supported: FxCtr[i]_is_supported := ECX[i] || (EDX[4:0] > i);
EDXBits 04 - 00: Number of contiguous fixed-function performance counters starting from 0 (if Version ID >
1).
Bits 12 - 05: Bit width of fixed-function performance counters (if Version ID > 1).
Bits 14 - 13: Reserved = 0.
Bit 15: AnyThread deprecation.
Bits 31 - 16: Reserved = 0.
Extended Topology Enumeration Leaf
0BH
NOTES:
CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking for the existence
of Leaf 1FH before using leaf 0BH.
Most of Leaf 0BH output depends on the initial value in ECX.
The EDX output of leaf 0BH is always valid and does not vary with input value in ECX.
Output value in ECX[7:0] always equals input value in ECX[7:0].
Sub-leaf index 0 enumerates SMT level. Each subsequent higher sub-leaf index enumerates a higher-
level topological entity in hierarchical order.
For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0.
If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8], other input values with ECX >
n also return 0 in ECX[15:8].
EAXBits 04 - 00: Number of bits to shift right on x2APIC ID to get a unique topology ID of the next level type*.
All logical processors with the same next level ID share current level.
Bits 31 - 05: Reserved.
EBXBits 15 - 00: Number of logical processors at this level type. The number reflects configuration as shipped
by Intel**.
Bits 31- 16: Reserved.
ECXBits 07 - 00: Level number. Same value in ECX input.
Bits 15 - 08: Level type***.
Bits 31 - 16: Reserved.
EDXBits 31- 00: x2APIC ID the current logical processor.
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
ValueInformation Provided about the Processor
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NOTES:
* Software should use this field (EAX[4:0]) to enumerate processor topology of the system.
** Software must not use EBX[15:0] to enumerate processor topology of the system. This value in this
field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual number of logical processors
available to BIOS/OS/Applications may be different from the value of EBX[15:0], depending on software
and platform hardware configurations.
*** The value of the “level type” field is not related to level numbers in any way, higher “level type” val-
ues do not mean higher levels. Level type field has the following encoding:
0: Invalid.
1: SMT.
2: Core.
3-255: Reserved.
Processor Extended State Enumeration Main Leaf (EAX = 0DH, ECX = 0)
0DH
NOTES:
Leaf 0DH main leaf (ECX = 0).
EAXBits 31 - 00: Reports the supported bits of the lower 32 bits of XCR0. XCR0[n] can be set to 1 only if
EAX[n] is 1.
Bit 00: x87 state.
Bit 01: SSE state.
Bit 02: AVX state.
Bits 04 - 03: MPX state.
Bits 07 - 05: AVX-512 state.
Bit 08: Used for IA32_XSS.
Bit 09: PKRU state.
Bits 12 - 10: Reserved.
Bit 13: Used for IA32_XSS.
Bits 15 - 14: Reserved.
Bit 16: Used for IA32_XSS.
Bits 31 - 17: Reserved.
EBXBits 31 - 00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) required by
enabled features in XCR0. May be different than ECX if some features at the end of the XSAVE save area
are not enabled.
ECXBit 31 - 00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) of the
XSAVE/XRSTOR save area required by all supported features in the processor, i.e., all the valid bit fields in
XCR0.
EDXBit 31 - 00: Reports the supported bits of the upper 32 bits of XCR0. XCR0[n+32] can be set to 1 only if
EDX[n] is 1.
Bits 31 - 00: Reserved.
Processor Extended State Enumeration Sub-leaf (EAX = 0DH, ECX = 1)
0DHEAXBit 00: XSAVEOPT is available.
Bit 01: Supports XSAVEC and the compacted form of XRSTOR if set.
Bit 02: Supports XGETBV with ECX = 1 if set.
Bit 03: Supports XSAVES/XRSTORS and IA32_XSS if set.
Bits 31 - 04: Reserved.
EBXBits 31 - 00: The size in bytes of the XSAVE area containing all states enabled by XCRO | IA32_XSS.
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
ValueInformation Provided about the Processor
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ECXBits 31 - 00: Reports the supported bits of the lower 32 bits of the IA32_XSS MSR. IA32_XSS[n] can be
set to 1 only if ECX[n] is 1.
Bits 07 - 00: Used for XCR0.
Bit 08: PT state.
Bit 09: Used for XCR0.
Bit 10: Reserved.
Bit 11: CET user state.
Bit 12: CET supervisor state.
Bit 13: HDC state.
Bit 14: Reserved.
Bit 15: LBR state (architectural).
Bit 16: HWP state.
Bits 31 - 17: Reserved.
EDX Bits 31 - 00: Reports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n+32] can
be set to 1 only if EDX[n] is 1.
Bits 31 - 00: Reserved.
Processor Extended State Enumeration Sub-leaves (EAX = 0DH, ECX = n, n > 1)
0DH
NOTES:
Leaf 0DH output depends on the initial value in ECX.
Each sub-leaf index (starting at position 2) is supported if it corresponds to a supported bit in either the
XCR0 register or the IA32_XSS MSR.
* If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf n (0
≤
n
≤
31) is invalid
if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1 returns 0 in ECX[n]. Sub-leaf n (32
≤
n
≤
63) is invalid if
sub-leaf 0 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].
EAXBits 31 - 0: The size in bytes (from the offset specified in EBX) of the save area for an extended state
feature associated with a valid sub-leaf index,
n
.
EBXBits 31 - 0: The offset in bytes of this extended state component’s save area from the beginning of the
XSAVE/XRSTOR area.
This field reports 0 if the sub-leaf index, n, does not map to a valid bit in the XCR0 register*.
ECXBit 00 is set if the bit n (corresponding to the sub-leaf index) is supported in the IA32_XSS MSR; it is clear
if bit n is instead supported in XCR0.
Bit 01 is set if, when the compacted format of an XSAVE area is used, this extended state component
located on the next 64-byte boundary following the preceding state component (otherwise, it is located
immediately following the preceding state component).
Bits 31 - 02 are reserved.
This field reports 0 if the sub-leaf index, n, is invalid*.
EDXThis field reports 0 if the sub-leaf index,
n
, is invalid*; otherwise it is reserved.
Intel Resource Director Technology (Intel RDT) Monitoring Enumeration Sub-leaf (EAX = 0FH, ECX = 0)
0FH
NOTES:
Leaf 0FH output depends on the initial value in ECX.
Sub-leaf index 0 reports valid resource type starting at bit position 1 of EDX.
EAXReserved.
EBXBits 31 - 00: Maximum range (zero-based) of RMID within this physical processor of all types.
ECXReserved.
EDXBit 00: Reserved.
Bit 01: Supports L3 Cache Intel RDT Monitoring if 1.
Bits 31 - 02: Reserved.
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
ValueInformation Provided about the Processor
image/svg+xml
L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf (EAX = 0FH, ECX = 1)
0FH
NOTES:
Leaf 0FH output depends on the initial value in ECX.
EAXReserved.
EBXBits 31 - 00: Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes) and Mem-
ory Bandwidth Monitoring (MBM) metrics.
ECXMaximum range (zero-based) of RMID of this resource type.
EDXBit 00: Supports L3 occupancy monitoring if 1.
Bit 01: Supports L3 Total Bandwidth monitoring if 1.
Bit 02: Supports L3 Local Bandwidth monitoring if 1.
Bits 31 - 03: Reserved.
Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf (EAX = 10H, ECX = 0)
10H
NOTES:
Leaf 10H output depends on the initial value in ECX.
Sub-leaf index 0 reports valid resource identification (ResID) starting at bit position 1 of EBX.
EAXReserved.
EBXBit 00: Reserved.
Bit 01: Supports L3 Cache Allocation Technology if 1.
Bit 02: Supports L2 Cache Allocation Technology if 1.
Bit 03: Supports Memory Bandwidth Allocation if 1.
Bits 31 - 04: Reserved.
ECXReserved.
EDXReserved.
L3 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID =1)
10H
NOTES:
Leaf 10H output depends on the initial value in ECX.
EAXBits 04 - 00: Length of the capacity bit mask for the corresponding ResID. Add one to the return value to
get the result.
Bits 31 - 05: Reserved.
EBXBits 31 - 00: Bit-granular map of isolation/contention of allocation units.
ECXBits 01- 00: Reserved.
Bit 02: Code and Data Prioritization Technology supported if 1.
Bits 31 - 03: Reserved.
EDXBits 15 - 00: Highest COS number supported for this ResID.
Bits 31 - 16: Reserved.
L2 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID =2)
10H
NOTES:
Leaf 10H output depends on the initial value in ECX.
EAXBits 04 - 00: Length of the capacity bit mask for the corresponding ResID. Add one to the return value to
get the result.
Bits 31 - 05: Reserved.
EBXBits 31 - 00: Bit-granular map of isolation/contention of allocation units.
ECXBits 31 - 00: Reserved.
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
ValueInformation Provided about the Processor
image/svg+xml
EDXBits 15 - 00: Highest COS number supported for this ResID.
Bits 31 - 16: Reserved.
Memory Bandwidth Allocation Enumeration Sub-leaf (EAX = 10H, ECX = ResID =3)
10H
NOTES:
Leaf 10H output depends on the initial value in ECX.
EAXBits 11 - 00: Reports the maximum MBA throttling value supported for the corresponding ResID. Add one
to the return value to get the result.
Bits 31 - 12: Reserved.
EBXBits 31 - 00: Reserved.
ECXBits 01 - 00: Reserved.
Bit 02: Reports whether the response of the delay values is linear.
Bits 31 - 03: Reserved.
EDXBits 15 - 00: Highest COS number supported for this ResID.
Bits 31 - 16: Reserved.
Intel SGX Capability Enumeration Leaf, sub-leaf 0 (EAX = 12H, ECX = 0)
12H
NOTES:
Leaf 12H sub-leaf 0 (ECX = 0) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1.
EAXBit 00: SGX1. If 1, Indicates Intel SGX supports the collection of SGX1 leaf functions.
Bit 01: SGX2. If 1, Indicates Intel SGX supports the collection of SGX2 leaf functions.
Bits 04 - 02: Reserved.
Bit 05: If 1, indicates Intel SGX supports ENCLV instruction leaves EINCVIRTCHILD, EDECVIRTCHILD, and
ESETCONTEXT.
Bit 06: If 1, indicates Intel SGX supports ENCLS instruction leaves ETRACKC, ERDINFO, ELDBC, and ELDUC.
Bits 31 - 07: Reserved.
EBXBits 31 - 00: MISCSELECT. Bit vector of supported extended SGX features.
ECXBits 31 - 00: Reserved.
EDXBits 07 - 00: MaxEnclaveSize_Not64. The maximum supported enclave size in non-64-bit mode is
2^(EDX[7:0]).
Bits 15 - 08: MaxEnclaveSize_64. The maximum supported enclave size in 64-bit mode is 2^(EDX[15:8]).
Bits 31 - 16: Reserved.
Intel SGX Attributes Enumeration Leaf, sub-leaf 1 (EAX = 12H, ECX = 1)
12H
NOTES:
Leaf 12H sub-leaf 1 (ECX = 1) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1.
EAXBit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[31:0] that software can set with ECREATE.
EBXBit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[63:32] that software can set with ECREATE.
ECXBit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[95:64] that software can set with ECREATE.
EDXBit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[127:96] that software can set with ECREATE.
Intel SGX EPC Enumeration Leaf, sub-leaves (EAX = 12H, ECX = 2 or higher)
12H
NOTES:
Leaf 12H sub-leaf 2 or higher (ECX >= 2) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1.
For sub-leaves (ECX = 2 or higher), definition of EDX,ECX,EBX,EAX[31:4] depends on the sub-leaf type
listed below.
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
ValueInformation Provided about the Processor
image/svg+xml
EAXBit 03 - 00: Sub-leaf Type
0000b: Indicates this sub-leaf is invalid.
0001b: This sub-leaf enumerates an EPC section. EBX:EAX and EDX:ECX provide information on the
Enclave Page Cache (EPC) section.
All other type encodings are reserved.
Type0000b. This sub-leaf is invalid.
EDX:ECX:EBX:EAX return 0.
Type0001b. This sub-leaf enumerates an EPC sections with EDX:ECX, EBX:EAX defined as follows.
EAX[11:04]: Reserved (enumerate 0).
EAX[31:12]: Bits 31:12 of the physical address of the base of the EPC section.
EBX[19:00]: Bits 51:32 of the physical address of the base of the EPC section.
EBX[31:20]: Reserved.
ECX[03:00]: EPC section property encoding defined as follows:
If ECX[3:0] = 0000b, then all bits of the EDX:ECX pair are enumerated as 0.
If ECX[3:0] = 0001b, then this section has confidentiality and integrity protection.
If ECX[3:0] = 0010b, then this section has confidentiality protection only.
All other encodings are reserved.
ECX[11:04]: Reserved (enumerate 0).
ECX[31:12]: Bits 31:12 of the size of the corresponding EPC section within the Processor Reserved
Memory.
EDX[19:00]: Bits 51:32 of the size of the corresponding EPC section within the Processor Reserved
Memory.
EDX[31:20]: Reserved.
Intel Processor Trace Enumeration Main Leaf (EAX = 14H, ECX = 0)
14H
NOTES:
Leaf 14H main leaf (ECX = 0).
EAXBits 31 - 00: Reports the maximum sub-leaf supported in leaf 14H.
EBXBit 00: If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1, and that IA32_RTIT_CR3_MATCH
MSR can be accessed.
Bit 01: If 1, indicates support of Configurable PSB and Cycle-Accurate Mode.
Bit 02: If 1, indicates support of IP Filtering, TraceStop filtering, and preservation of Intel PT MSRs across
warm reset.
Bit 03: If 1, indicates support of MTC timing packet and suppression of COFI-based packets.
Bit 04: If 1, indicates support of PTWRITE. Writes can set IA32_RTIT_CTL[12] (PTWEn) and
IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE can generate packets.
Bit 05: If 1, indicates support of Power Event Trace. Writes can set IA32_RTIT_CTL[4] (PwrEvtEn),
enabling Power Event Trace packet generation.
Bit 06: If 1, indicates support for PSB and PMI preservation. Writes can set IA32_RTIT_CTL[56] (InjectPsb-
PmiOnEnable), enabling the processor to set IA32_RTIT_STATUS[7] (PendTopaPMI) and/or
IA32_RTIT_STATUS[6] (PendPSB) in order to preserve ToPA PMIs and/or PSBs otherwise lost due to Intel
PT disable. Writes can also set PendToPAPMI and PendPSB.
Bit 07: If 1, writes can set IA32_RTIT_CTL[31] (EventEn), enabling Event Trace packet generation.
Bit 08: If 1, writes can set IA32_RTIT_CTL[55] (DisTNT), disabling TNT packet generation.
Bit 31 - 09: Reserved.
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
ValueInformation Provided about the Processor
image/svg+xml
ECXBit 00: If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence utilizing the ToPA output
scheme; IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
Bit 01: If 1, ToPA tables can hold any number of output entries, up to the maximum allowed by the Mas-
kOrTableOffset field of IA32_RTIT_OUTPUT_MASK_PTRS.
Bit 02: If 1, indicates support of Single-Range Output scheme.
Bit 03: If 1, indicates support of output to Trace Transport subsystem.
Bit 30 - 04: Reserved.
Bit 31: If 1, generated packets which contain IP payloads have LIP values, which include the CS base com-
ponent.
EDXBits 31 - 00: Reserved.
Intel Processor Trace Enumeration Sub-leaf (EAX = 14H, ECX = 1)
14HEAXBits 02 - 00: Number of configurable Address Ranges for filtering.
Bits 15 - 03: Reserved.
Bits 31 - 16: Bitmap of supported MTC period encodings.
EBXBits 15 - 00: Bitmap of supported Cycle Threshold value encodings.
Bit 31 - 16: Bitmap of supported Configurable PSB frequency encodings.
ECXBits 31 - 00: Reserved.
EDX Bits 31 - 00: Reserved.
Time Stamp Counter and Nominal Core Crystal Clock Information Leaf
15H
NOTES:
If EBX[31:0] is 0, the TSC/”core crystal clock” ratio is not enumerated.
EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core crystal clock frequency.
If ECX is 0, the nominal core crystal clock frequency is not enumerated.
“TSC frequency” = “core crystal clock frequency” * EBX/EAX.
The core crystal clock may differ from the reference clock, bus clock, or core clock frequencies.
EAXBits 31 - 00: An unsigned integer which is the denominator of the TSC/”core crystal clock” ratio.
EBXBits 31 - 00: An unsigned integer which is the numerator of the TSC/”core crystal clock” ratio.
ECXBits 31 - 00: An unsigned integer which is the nominal frequency of the core crystal clock in Hz.
EDXBits 31 - 00: Reserved = 0.
Processor Frequency Information Leaf
16HEAXBits 15 - 00: Processor Base Frequency (in MHz).
Bits 31 - 16: Reserved =0.
EBXBits 15 - 00: Maximum Frequency (in MHz).
Bits 31 - 16: Reserved = 0.
ECXBits 15 - 00: Bus (Reference) Frequency (in MHz).
Bits 31 - 16: Reserved = 0.
EDXReserved.
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
ValueInformation Provided about the Processor
image/svg+xml
NOTES:
* Data is returned from this interface in accordance with the processor's specification and does not reflect
actual values. Suitable use of this data includes the display of processor information in like manner to the
processor brand string and for determining the appropriate range to use when displaying processor
information e.g. frequency history graphs. The returned information should not be used for any other
purpose as the returned information does not accurately correlate to information / counters returned by
other processor interfaces.
While a processor may support the Processor Frequency Information leaf, fields that return a value of
zero are not supported.
System-On-Chip Vendor Attribute Enumeration Main Leaf (EAX = 17H, ECX = 0)
17H
NOTES:
Leaf 17H main leaf (ECX = 0).
Leaf 17H output depends on the initial value in ECX.
Leaf 17H sub-leaves 1 through 3 reports SOC Vendor Brand String.
Leaf 17H is valid if MaxSOCID_Index >= 3.
Leaf 17H sub-leaves 4 and above are reserved.
EAXBits 31 - 00: MaxSOCID_Index. Reports the maximum input value of supported sub-leaf in leaf 17H.
EBXBits 15 - 00: SOC Vendor ID.
Bit 16: IsVendorScheme. If 1, the SOC Vendor ID field is assigned via an industry standard enumeration
scheme. Otherwise, the SOC Vendor ID field is assigned by Intel.
Bits 31 - 17: Reserved = 0.
ECXBits 31 - 00: Project ID. A unique number an SOC vendor assigns to its SOC projects.
EDXBits 31 - 00: Stepping ID. A unique number within an SOC project that an SOC vendor assigns.
System-On-Chip Vendor Attribute Enumeration Sub-leaf (EAX = 17H, ECX = 1..3)
17HEAXBit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.
EBXBit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.
ECXBit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.
EDXBit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.
NOTES:
Leaf 17H output depends on the initial value in ECX.
SOC Vendor Brand String is a UTF-8 encoded string padded with trailing bytes of 00H.
The complete SOC Vendor Brand String is constructed by concatenating in ascending order of
EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.
System-On-Chip Vendor Attribute Enumeration Sub-leaves (EAX = 17H, ECX > MaxSOCID_Index)
17H
NOTES:
Leaf 17H output depends on the initial value in ECX.
EAXBits 31 - 00: Reserved = 0.
EBXBits 31 - 00: Reserved = 0.
ECXBits 31 - 00: Reserved = 0.
EDXBits 31 - 00: Reserved = 0.
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
ValueInformation Provided about the Processor
image/svg+xml
Deterministic Address Translation Parameters Main Leaf (EAX = 18H, ECX = 0)
18H
NOTES:
Each sub-leaf enumerates a different address translation structure.
If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n
exceeds the value that sub-leaf 0 returns in EAX. A sub-leaf index is also invalid if EDX[4:0] returns 0.
Valid sub-leaves do not need to be contiguous or in any particular order. A valid sub-leaf may be in a
higher input ECX value than an invalid sub-leaf or than a valid sub-leaf of a higher or lower-level struc-
ture.
* Some unified TLBs will allow a single TLB entry to satisfy data read/write and instruction fetches.
Others will require separate entries (e.g., one loaded on data read/write and another loaded on an
instruction fetch) . Please see the
Intel® 64 and IA-32 Architectures Optimization Reference Manual
for
details of a particular product.
** Add one to the return value to get the result.
EAXBits 31 - 00: Reports the maximum input value of supported sub-leaf in leaf 18H.
EBXBit 00: 4K page size entries supported by this structure.
Bit 01: 2MB page size entries supported by this structure.
Bit 02: 4MB page size entries supported by this structure.
Bit 03: 1 GB page size entries supported by this structure.
Bits 07 - 04: Reserved.
Bits 10 - 08: Partitioning (0: Soft partitioning between the logical processors sharing this structure).
Bits 15 - 11: Reserved.
Bits 31 - 16: W = Ways of associativity.
ECXBits 31 - 00: S = Number of Sets.
EDXBits 04 - 00: Translation cache type field.
00000b: Null (indicates this sub-leaf is not valid).
00001b: Data TLB.
00010b: Instruction TLB.
00011b: Unified TLB*.
00100b: Load Only TLB. Hit on loads; fills on both loads and stores.
00101b: Store Only TLB. Hit on stores; fill on stores.
All other encodings are reserved.
Bits 07 - 05: Translation cache level (starts at 1).
Bit 08: Fully associative structure.
Bits 13 - 09: Reserved.
Bits 25- 14: Maximum number of addressable IDs for logical processors sharing this translation cache**
Bits 31 - 26: Reserved.
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
ValueInformation Provided about the Processor
image/svg+xml
Deterministic Address Translation Parameters Sub-leaf (EAX = 18H, ECX
≥
1)
18H
NOTES:
Each sub-leaf enumerates a different address translation structure.
If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n
exceeds the value that sub-leaf 0 returns in EAX. A sub-leaf index is also invalid if EDX[4:0] returns 0.
Valid sub-leaves do not need to be contiguous or in any particular order. A valid sub-leaf may be in a
higher input ECX value than an invalid sub-leaf or than a valid sub-leaf of a higher or lower-level struc-
ture.
* Some unified TLBs will allow a single TLB entry to satisfy data read/write and instruction fetches.
Others will require separate entries (e.g., one loaded on data read/write and another loaded on an
instruction fetch. See the
Intel® 64 and IA-32 Architectures Optimization Reference Manual
for details
of a particular product.
** Add one to the return value to get the result.
EAXBits 31 - 00: Reserved.
EBXBit 00: 4K page size entries supported by this structure.
Bit 01: 2MB page size entries supported by this structure.
Bit 02: 4MB page size entries supported by this structure.
Bit 03: 1 GB page size entries supported by this structure.
Bits 07 - 04: Reserved.
Bits 10 - 08: Partitioning (0: Soft partitioning between the logical processors sharing this structure).
Bits 15 - 11: Reserved.
Bits 31 - 16: W = Ways of associativity.
ECXBits 31 - 00: S = Number of Sets.
EDXBits 04 - 00: Translation cache type field.
0000b: Null (indicates this sub-leaf is not valid).
0001b: Data TLB.
0010b: Instruction TLB.
0011b: Unified TLB*.
All other encodings are reserved.
Bits 07 - 05: Translation cache level (starts at 1).
Bit 08: Fully associative structure.
Bits 13 - 09: Reserved.
Bits 25- 14: Maximum number of addressable IDs for logical processors sharing this translation cache**
Bits 31 - 26: Reserved.
Key Locker Leaf (EAX = 19H)
19H
EAXBit 00: Key Locker restriction of CPL0-only supported.
Bit 01: Key Locker restriction of no-encrypt supported.
Bit 02: Key Locker restriction of no-decrypt supported.
Bits 31-03: Reserved.
EBXBit 00: AESKLE. If 1, the AES Key Locker instructions are fully enabled.
Bit 01: Reserved.
Bit 02: If 1, the AES wide Key Locker instructions are supported.
Bit 03: Reserved.
Bit 04: If 1, the platform supports the Key Locker MSRs (IA32_COPY_LOCAL_TO_PLATFORM,
IA23_COPY_PLATFORM_TO_LOCAL, IA32_COPY_STATUS, and IA32_IWKEYBACKUP_STATUS) and backing
up the internal wrapping key.
Bits 31-05: Reserved.
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
ValueInformation Provided about the Processor
image/svg+xml
ECXBit 00: If 1, the NoBackup parameter to LOADIWKEY is supported.
Bit 01: If 1, KeySource encoding of 1 (randomization of the internal wrapping key) is supported.
Bits 31- 02: Reserved.
EDXReserved.
Hybrid Information Enumeration Leaf (EAX = 1AH, ECX = 0)
1AH
EAXEnumerates the native model ID and core type.
Bits 31-24: Core type
10H: Reserved
20H: Intel Atom®
30H: Reserved
40H: Intel® Core™
Bits 23-0: Native model ID of the core. The core-type and native mode ID can be used to uniquely identify
the microarchitecture of the core. This native model ID is not unique across core types, and not related to
the model ID reported in CPUID leaf 01H, and does not identify the SOC.
EBXReserved.
ECXReserved.
EDXReserved.
PCONFIG Information Sub-leaf (EAX = 1BH, ECX
≥
0)
1BH
For details on this sub-leaf, see “INPUT EAX = 1BH: Returns PCONFIG Information” on page 3-247.
NOTE:
Leaf 1BH is supported if CPUID.(EAX=07H, ECX=0H):EDX[18] = 1.
Last Branch Records Information Leaf (EAX = 1CH, ECX = 0)
1CH
NOTES:
This leaf pertains to the architectural feature.
For leaf 01CH, CPUID will ignore the ECX value.
EAXBits 07 - 00: Supported LBR Depth Values. For each bit n set in this field, the IA32_LBR_DEPTH.DEPTH
value 8*(n+1) is supported.
Bits 29 - 08: Reserved.
Bit 30: Deep C-state Reset. If set, indicates that LBRs may be cleared on an MWAIT that requests a C-state
numerically greater than C1.
Bit 31: IP Values Contain LIP. If set, LBR IP values contain LIP. If clear, IP values contain Effective IP.
EBXBit 00: CPL Filtering Supported. If set, the processor supports setting IA32_LBR_CTL[2:1] to non-zero
value.
Bit 01: Branch Filtering Supported. If set, the processor supports setting IA32_LBR_CTL[22:16] to non-
zero value.
Bit 02: Call-stack Mode Supported. If set, the processor supports setting IA32_LBR_CTL[3] to 1.
Bits 31 - 03: Reserved.
ECXBit 00: Mispredict Bit Supported. IA32_LBR_x_INFO[63] holds indication of branch misprediction
(MISPRED).
Bit 01: Timed LBRs Supported. IA32_LBR_x_INFO[15:0] holds CPU cycles since last LBR entry (CYC_CNT),
and IA32_LBR_x_INFO[60] holds an indication of whether the value held there is valid (CYC_CNT_VALID).
Bit 02: Branch Type Field Supported. IA32_LBR_INFO_x[59:56] holds indication of the recorded
operation's branch type (BR_TYPE).
Bits 31 - 03: Reserved.
EDXBits 31 - 00: Reserved.
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
ValueInformation Provided about the Processor
image/svg+xml
V2 Extended Topology Enumeration Leaf
1FH
NOTES:
CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking for the existence
of Leaf 1FH and using this if available.
Most of Leaf 1FH output depends on the initial value in ECX.
The EDX output of leaf 1FH is always valid and does not vary with input value in ECX.
Output value in ECX[7:0] always equals input value in ECX[7:0].
Sub-leaf index 0 enumerates SMT level. Each subsequent higher sub-leaf index enumerates a higher-
level topological entity in hierarchical order.
For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0.
If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8], other input values with ECX >
n also return 0 in ECX[15:8].
EAXBits 04 - 00: Number of bits to shift right on x2APIC ID to get a unique topology ID of the next level type*.
All logical processors with the same next level ID share current level.
Bits 31 - 05: Reserved.
EBXBits 15 - 00: Number of logical processors at this level type. The number reflects configuration as shipped
by Intel**.
Bits 31- 16: Reserved.
ECXBits 07 - 00: Level number. Same value in ECX input.
Bits 15 - 08: Level type***.
Bits 31 - 16: Reserved.
EDXBits 31- 00: x2APIC ID the current logical processor.
NOTES:
* Software should use this field (EAX[4:0]) to enumerate processor topology of the system.
** Software must not use EBX[15:0] to enumerate processor topology of the system. This value in this
field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual number of logical processors
available to BIOS/OS/Applications may be different from the value of EBX[15:0], depending on software
and platform hardware configurations.
*** The value of the “level type” field is not related to level numbers in any way, higher “level type” val-
ues do not mean higher levels. Level type field has the following encoding:
0: Invalid.
1: SMT.
2: Core.
3: Module.
4: Tile.
5: Die.
6-255: Reserved.
Processor History Reset Sub-leaf (EAX = 20H, ECX = 0)
20H
EAXReports the maximum number of sub-leaves that are supported in leaf 20H.
EBXIndicates which bits may be set in the IA32_HRESET_ENABLE MSR to enable reset of different compo-
nents of hardware-maintained history.
Bit 00: Indicates support for both HRESET’s EAX[0] parameter, and IA32_HRESET_ENABLE[0] set by the
OS to enable reset of Intel® Thread Director history.
Bits 31-01: Reserved = 0.
ECXReserved.
EDXReserved.
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
ValueInformation Provided about the Processor
image/svg+xml
Unimplemented CPUID Leaf Functions
21HInvalid. No existing or future CPU will return processor identification or feature information if the initial
EAX value is 21H. If the value returned by CPUID.0:EAX (the maximum input value for basic CPUID
information) is at least 21H, 0 is returned in the registers EAX, EBX, ECX, and EDX. Otherwise, the data
for the highest basic information leaf is returned.
40000000H
-
4FFFFFFFH
Invalid. No existing or future CPU will return processor identification or feature information if the initial
EAX value is in the range 40000000H to 4FFFFFFFH.
Extended Function CPUID Information
80000000HEAXMaximum Input Value for Extended Function CPUID Information.
EBXReserved.
ECXReserved.
EDXReserved.
80000001HEAXExtended Processor Signature and Feature Bits.
EBXReserved.
ECXBit 00: LAHF/SAHF available in 64-bit mode.*
Bits 04 - 01: Reserved.
Bit 05: LZCNT.
Bits 07 - 06: Reserved.
Bit 08: PREFETCHW.
Bits 31 - 09: Reserved.
EDXBits 10 - 00: Reserved.
Bit 11: SYSCALL/SYSRET.**
Bits 19 - 12: Reserved = 0.
Bit 20: Execute Disable Bit available.
Bits 25 - 21: Reserved = 0.
Bit26: 1-GByte pages are available if 1.
Bit 27: RDTSCP and IA32_TSC_AUX are available if 1.
Bit 28: Reserved = 0.
Bit 29: Intel
®
64 Architecture available if 1.
Bits 31 - 30: Reserved = 0.
NOTES:
* LAHF and SAHF are always available in other modes, regardless of the enumeration of this feature flag.
** Intel processors support SYSCALL and SYSRET only in 64-bit mode. This feature flag is always enumer-
ated as 0 outside 64-bit mode.
80000002HEAX
EBX
ECX
EDX
Processor Brand String.
Processor Brand String Continued.
Processor Brand String Continued.
Processor Brand String Continued.
80000003HEAX
EBX
ECX
EDX
Processor Brand String Continued.
Processor Brand String Continued.
Processor Brand String Continued.
Processor Brand String Continued.
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
ValueInformation Provided about the Processor
image/svg+xml
INPUT EAX = 0: Returns CPUID’s Highest Value for Basic Processor Information and the Vendor Identification String
When CPUID executes with EAX set to 0, the processor returns the highest value the CPUID recognizes for
returning basic processor information. The value is returned in the EAX register and is processor specific.
80000004HEAX
EBX
ECX
EDX
Processor Brand String Continued.
Processor Brand String Continued.
Processor Brand String Continued.
Processor Brand String Continued.
80000005HEAX
EBX
ECX
EDX
Reserved = 0.
Reserved = 0.
Reserved = 0.
Reserved = 0.
80000006HEAX
EBX
Reserved = 0.
Reserved = 0.
ECX
EDX
Bits 07 - 00: Cache Line size in bytes.
Bits 11 - 08: Reserved.
Bits 15 - 12: L2 Associativity field *.
Bits 31 - 16: Cache size in 1K units.
Reserved = 0.
NOTES:
*
L2 associativity field encodings:
00H - Disabled08H - 16 ways
01H - 1 way (direct mapped) 09H - Reserved
02H - 2 ways 0AH - 32 ways
03H - Reserved0BH - 48 ways
04H - 4 ways0CH - 64 ways
05H - Reserved0DH - 96 ways
06H - 8 ways0EH - 128 ways
07H - See CPUID leaf 04H, sub-leaf 2**0FH - Fully associative
** CPUID leaf 04H provides details of deterministic cache parameters, including the L2 cache in sub-leaf 2
80000007HEAX
EBX
ECX
EDX
Reserved = 0.
Reserved = 0.
Reserved = 0.
Bits 07 - 00: Reserved = 0.
Bit 08: Invariant TSC available if 1.
Bits 31 - 09: Reserved = 0.
80000008HEAXLinear/Physical Address size.
Bits 07 - 00: #Physical Address Bits*.
Bits 15 - 08: #Linear Address Bits.
Bits 31 - 16: Reserved = 0.
EBX
ECX
EDX
Bits 08-00: Reserved = 0.
Bit 09: WBNOINVD is available if 1.
Bits 31-10: Reserved = 0.
Reserved = 0.
Reserved = 0.
NOTES:
* If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address number supported should
come from this field.
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
ValueInformation Provided about the Processor
image/svg+xml
A vendor identification string is also returned in EBX, EDX, and ECX. For Intel processors, the string is “Genuin-
eIntel” and is expressed:
EBX := 756e6547h (* “Genu”, with G in the low eight bits of BL *)
EDX := 49656e69h (* “ineI”, with i in the low eight bits of DL *)
ECX := 6c65746eh (* “ntel”, with n in the low eight bits of CL *)
INPUT EAX = 80000000H: Returns CPUID’s Highest Value for Extended Processor Information
When CPUID executes with EAX set to 80000000H, the processor returns the highest value the processor recog-
nizes for returning extended processor information. The value is returned in the EAX register and is processor
specific.
IA32_BIOS_SIGN_ID Returns Microcode Update Signature
For processors that support the microcode update facility, the IA32_BIOS_SIGN_ID MSR is loaded with the update
signature whenever CPUID executes. The signature is returned in the upper DWORD. For details, see Chapter 9 in
the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A
.
INPUT EAX = 01H: Returns Model, Family, Stepping Information
When CPUID executes with EAX set to 01H, version information is returned in EAX (see Figure3-6). For example:
model, family, and processor type for the Intel Xeon processor 5100 series is as follows:
•
Model — 1111B
•
Family — 0101B
•
Processor Type — 00B
See Table 3-9 for available processor type values. Stepping IDs are provided as needed.
Figure 3-6. Version Information Returned by CPUID in EAX
OM16525
Processor Type
034781112131415161920272831
EAX
Family (0FH for the Pentium 4 Processor Family)
Model
Extended
Family ID
Extended
Model ID
Family
ID
Model
Stepping
ID
Extended Family ID (0)
Extended Model ID (0)
Reserved
image/svg+xml
NOTE
See Chapter 20 in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1
,
for information on identifying earlier IA-32 processors.
The Extended Family ID needs to be examined only when the Family ID is 0FH. Integrate the fields into a display
using the following rule:
IF Family_ID
≠
0FH
THEN DisplayFamily = Family_ID;
ELSE DisplayFamily = Extended_Family_ID + Family_ID;
(* Right justify and zero-extend 4-bit field. *)
FI;
(* Show DisplayFamily as HEX field. *)
The Extended Model ID needs to be examined only when the Family ID is 06H or 0FH. Integrate the field into a
display using the following rule:
IF (Family_ID = 06H or Family_ID = 0FH)
THEN DisplayModel = (Extended_Model_ID « 4) + Model_ID;
(* Right justify and zero-extend 4-bit field; display Model_ID as HEX field.*)
ELSE DisplayModel = Model_ID;
FI;
(* Show DisplayModel as HEX field. *)
INPUT EAX = 01H: Returns Additional Information in EBX
When CPUID executes with EAX set to 01H, additional information is returned to the EBX register:
•
Brand index (low byte of EBX) — this number provides an entry into a brand string table that contains brand
strings for IA-32 processors. More information about this field is provided later in this section.
•
CLFLUSH instruction cache line size (second byte of EBX) — this number indicates the size of the cache line
flushed by the CLFLUSH and CLFLUSHOPT instructions in 8-byte increments. This field was introduced in the
Pentium 4 processor.
•
Local APIC ID (high byte of EBX) — this number is the 8-bit ID that is assigned to the local APIC on the
processor during power up. This field was introduced in the Pentium 4 processor.
INPUT EAX = 01H: Returns Feature Information in ECX and EDX
When CPUID executes with EAX set to 01H, feature information is returned in ECX and EDX.
•
Figure3-7 and Table 3-10 show encodings for ECX.
•
Figure3-8 and Table 3-11 show encodings for EDX.
For all feature flags, a 1 indicates that the feature is supported. Use Intel to properly interpret feature flags.
NOTE
Software must confirm that a processor feature is present using feature flags returned by CPUID
prior to using the feature. Software should not depend on future offerings retaining all features.
Table 3-9. Processor Type Field
TypeEncoding
Original OEM Processor00B
Intel OverDrive
®
Processor01B
Dual processor (not applicable to Intel486 processors)10B
Intel reserved11B
image/svg+xml
Figure 3-7. Feature Information Returned in the ECX Register
Table 3-10. Feature Information Returned in the ECX Register
Bit # Mnemonic Description
0 SSE3
Streaming SIMD Extensions 3 (SSE3).
A value of 1 indicates the processor supports this
technology.
1PCLMULQDQ
PCLMULQDQ.
A value of 1 indicates the processor supports the PCLMULQDQ instruction.
2DTES64
64-bit DS Area.
A value of 1 indicates the processor supports DS area using 64-bit layout.
3 MONITOR
MONITOR/MWAIT.
A value of 1 indicates the processor supports this feature.
4 DS-CPL
CPL Qualified Debug Store.
A value of 1 indicates the processor supports the extensions to the
Debug Store feature to allow for branch message storage qualified by CPL.
5VMX
Virtual Machine Extensions.
A value of 1 indicates that the processor supports this technology.
6SMX
Safer Mode Extensions.
A value of 1 indicates that the processor supports this technology. See
Chapter 6, “Safer Mode Extensions Reference”.
7 EIST
Enhanced Intel SpeedStep® technology.
A value of 1 indicates that the processor supports this
technology.
8 TM2
Thermal Monitor 2.
A value of 1 indicates whether the processor supports this technology.
9SSSE3A value of 1 indicates the presence of the Supplemental Streaming SIMD Extensions 3 (SSSE3). A
value of 0 indicates the instruction extensions are not present in the processor.
OM16524b
CNXT-ID — L1 Context ID
012345678910111213141516171819202122232425262728293031
ECX
TM2 — Thermal Monitor 2
EIST — Enhanced Intel SpeedStep® Technology
DS-CPL — CPL Qualified Debug Store
MONITOR — MONITOR/MWAIT
PCLMULQDQ — Carryless Multiplication
Reserved
CMPXCHG16B
SMX — Safer Mode Extensions
xTPR Update Control
SSSE3 — SSSE3 Extensions
PDCM — Perf/Debug Capability MSR
VMX — Virtual Machine Extensions
SSE4_1 — SSE4.1
OSXSAVE
SSE4_2 — SSE4.2
DCA — Direct Cache Access
x2APIC
POPCNT
XSAVE
AVX
AES
FMA — Fused Multiply Add
SSE3 — SSE3 Extensions
PCID — Process-context Identifiers
0
DTES64 — 64-bit DS Area
MOVBE
TSC-Deadline
F16C
RDRAND
SDBG
image/svg+xml
10CNXT-ID
L1 Context ID.
A value of 1 indicates the L1 data cache mode can be set to either adaptive mode
or shared mode. A value of 0 indicates this feature is not supported. See definition of the
IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for details.
11SDBGA value of 1 indicates the processor supports IA32_DEBUG_INTERFACE MSR for silicon debug.
12FMAA value of 1 indicates the processor supports FMA extensions using YMM state.
13CMPXCHG16B
CMPXCHG16B Available.
A value of 1 indicates that the feature is available. See the
“CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes” section in this chapter for a
description.
14xTPR Update
Control
xTPR Update Control.
A value of 1 indicates that the processor supports changing
IA32_MISC_ENABLE[bit 23].
15PDCM
Perfmon and Debug Capability:
A value of 1 indicates the processor supports the performance
and debug feature indication MSR IA32_PERF_CAPABILITIES.
16ReservedReserved
17PCID
Process-context identifiers.
A value of 1 indicates that the processor supports PCIDs and that
software may set CR4.PCIDE to 1.
18 DCA A value of 1 indicates the processor supports the ability to prefetch data from a memory mapped
device.
19SSE4_1A value of 1 indicates that the processor supports SSE4.1.
20SSE4_2A value of 1 indicates that the processor supports SSE4.2.
21x2APICA value of 1 indicates that the processor supports x2APIC feature.
22MOVBEA value of 1 indicates that the processor supports MOVBE instruction.
23POPCNTA value of 1 indicates that the processor supports the POPCNT instruction.
24TSC-DeadlineA value of 1 indicates that the processor’s local APIC timer supports one-shot operation using a
TSC deadline value.
25 AESNIA value of 1 indicates that the processor supports the AESNI instruction extensions.
26XSAVEA value of 1 indicates that the processor supports the XSAVE/XRSTOR processor extended states
feature, the XSETBV/XGETBV instructions, and XCR0.
27OSXSAVEA value of 1 indicates that the OS has set CR4.OSXSAVE[bit 18] to enable XSETBV/XGETBV
instructions to access XCR0 and to support processor extended state management using
XSAVE/XRSTOR.
28AVXA value of 1 indicates the processor supports the AVX instruction extensions.
29F16CA value of 1 indicates that processor supports 16-bit floating-point conversion instructions.
30RDRANDA value of 1 indicates that processor supports RDRAND instruction.
31 Not UsedAlways returns 0.
Table 3-10. Feature Information Returned in the ECX Register (Contd.)
Bit # Mnemonic Description
image/svg+xml
Figure 3-8. Feature Information Returned in the EDX Register
OM16523
PBE–Pend. Brk. EN.
012345678910111213141516171819202122232425262728293031
EDX
TM–Therm. Monitor
HTT–Multi-threading
SS–Self Snoop
SSE2–SSE2 Extensions
SSE–SSE Extensions
FXSR–FXSAVE/FXRSTOR
MMX–MMX Technology
ACPI–Thermal Monitor and Clock Ctrl
DS–Debug Store
CLFSH–CLFLUSH instruction
PSN–Processor Serial Number
PSE-36 – Page Size Extension
PAT–Page Attribute Table
CMOV–Conditional Move/Compare Instruction
MCA–Machine Check Architecture
PGE–PTE Global Bit
MTRR–Memory Type Range Registers
SEP–SYSENTER and SYSEXIT
APIC–APIC on Chip
CX8–CMPXCHG8B Inst.
MCE–Machine Check Exception
PAE–Physical Address Extensions
MSR–RDMSR and WRMSR Support
TSC–Time Stamp Counter
PSE–Page Size Extensions
DE–Debugging Extensions
VME–Virtual-8086 Mode Enhancement
FPU–x87 FPU on Chip
Reserved
image/svg+xml
Table 3-11. More on Feature Information Returned in the EDX Register
Bit # Mnemonic Description
0 FPU
Floating Point Unit On-Chip.
The processor contains an x87 FPU.
1 VME
Virtual 8086 Mode Enhancements.
Virtual 8086 mode enhancements, including CR4.VME for controlling the
feature, CR4.PVI for protected mode virtual interrupts, software interrupt indirection, expansion of the TSS
with the software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags.
2 DE
Debugging Extensions.
Support for I/O breakpoints, including CR4.DE for controlling the feature, and optional
trapping of accesses to DR4 and DR5.
3 PSE
Page Size Extension.
Large pages of size 4 MByte are supported, including CR4.PSE for controlling the
feature, the defined dirty bit in PDE (Page Directory Entries), optional reserved bit trapping in CR3, PDEs, and
PTEs.
4 TSC
Time Stamp Counter.
The RDTSC instruction is supported, including CR4.TSD for controlling privilege.
5 MSR
Model Specific Registers RDMSR and WRMSR Instructions.
The RDMSR and WRMSR instructions are
supported. Some of the MSRs are implementation dependent.
6 PAE
Physical Address Extension.
Physical addresses greater than 32 bits are supported: extended page table
entry formats, an extra level in the page translation tables is defined, 2-MByte pages are supported instead of
4 Mbyte pages if PAE bit is 1.
7 MCE
Machine Check Exception.
Exception 18 is defined for Machine Checks, including CR4.MCE for controlling the
feature. This feature does not define the model-specific implementations of machine-check error logging,
reporting, and processor shutdowns. Machine Check exception handlers may have to depend on processor
version to do model specific processing of the exception, or test for the presence of the Machine Check feature.
8 CX8
CMPXCHG8B Instruction.
The compare-and-exchange 8 bytes (64 bits) instruction is supported (implicitly
locked and atomic).
9 APIC
APIC On-Chip.
The processor contains an Advanced Programmable Interrupt Controller (APIC), responding to
memory mapped commands in the physical address range FFFE0000H to FFFE0FFFH (by default - some
processors permit the APIC to be relocated).
10 Reserved Reserved
11SEP
SYSENTER and SYSEXIT Instructions.
The SYSENTER and SYSEXIT and associated MSRs are supported.
12 MTRR
Memory Type Range Registers.
MTRRs are supported. The MTRRcap MSR contains feature bits that describe
what memory types are supported, how many variable MTRRs are supported, and whether fixed MTRRs are
supported.
13 PGE
Page Global Bit.
The global bit is supported in paging-structure entries that map a page, indicating TLB entries
that are common to different processes and need not be flushed. The CR4.PGE bit controls this feature.
14 MCA
Machine Check Architecture.
A value of 1 indicates the Machine Check Architecture of reporting machine
errors is supported. The MCG_CAP MSR contains feature bits describing how many banks of error reporting
MSRs are supported.
15 CMOV
Conditional Move Instructions.
The conditional move instruction CMOV is supported. In addition, if x87 FPU is
present as indicated by the CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported
16 PAT
Page Attribute Table.
Page Attribute Table is supported. This feature augments the Memory Type Range
Registers (MTRRs), allowing an operating system to specify attributes of memory accessed through a linear
address on a 4KB granularity.
17 PSE-36
36-Bit Page Size Extension.
4-MByte pages addressing physical memory beyond 4 GBytes are supported with
32-bit paging. This feature indicates that upper bits of the physical address of a 4-MByte page are encoded in
bits20:13 of the page-directory entry. Such physical addresses are limited by MAXPHYADDR and may be up to
40 bits in size.
18 PSN
Processor Serial Number.
The processor supports the 96-bit processor identification number feature and the
feature is enabled.
19 CLFSH
CLFLUSH Instruction.
CLFLUSH Instruction is supported.
20Reserved Reserved
image/svg+xml
INPUT EAX = 02H: TLB/Cache/Prefetch Information Returned in EAX, EBX, ECX, EDX
When CPUID executes with EAX set to 02H, the processor returns information about the processor’s internal TLBs,
cache and prefetch hardware in the EAX, EBX, ECX, and EDX registers. The information is reported in encoded form
and fall into the following categories:
•
The least-significant byte in register EAX (register AL) will always return 01H. Software should ignore this value
and not interpret it as an informational descriptor.
•
The most significant bit (bit 31) of each register indicates whether the register contains valid information (set
to 0) or is reserved (set to 1).
•
If a register contains valid information, the information is contained in 1 byte descriptors. There are four types
of encoding values for the byte descriptor, the encoding type is noted in the second column of Table 3-12. Table
3-12 lists the encoding of these descriptors. Note that the order of descriptors in the EAX, EBX, ECX, and EDX
registers is not defined; that is, specific bytes are not designated to contain descriptors for specific cache,
prefetch, or TLB types. The descriptors may appear in any order. Note also a processor may report a general
descriptor type (FFH) and not report any byte descriptor of “cache type” via CPUID leaf 2.
21 DS
Debug Store.
The processor supports the ability to write debug information into a memory resident buffer.
This feature is used by the branch trace store (BTS) and processor event-based sampling (PEBS) facilities (see
Chapter 23, “Introduction to Virtual-Machine Extensions,” in the
Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3C
).
22 ACPI
Thermal Monitor and Software Controlled Clock Facilities.
The processor implements internal MSRs that
allow processor temperature to be monitored and processor performance to be modulated in predefined duty
cycles under software control.
23 MMX
Intel MMX Technology.
The processor supports the Intel MMX technology.
24 FXSR
FXSAVE and FXRSTOR Instructions.
The FXSAVE and FXRSTOR instructions are supported for fast save and
restore of the floating point context. Presence of this bit also indicates that CR4.OSFXSR is available for an
operating system to indicate that it supports the FXSAVE and FXRSTOR instructions.
25 SSE
SSE.
The processor supports the SSE extensions.
26 SSE2
SSE2.
The processor supports the SSE2 extensions.
27SS
Self Snoop.
The processor supports the management of conflicting memory types by performing a snoop of its
own cache structure for transactions issued to the bus.
28HTT
Max APIC IDs reserved field is Valid.
A value of 0 for HTT indicates there is only a single logical processor in
the package and software should assume only a single APIC ID is reserved. A value of 1 for HTT indicates the
value in CPUID.1.EBX[23:16] (the Maximum number of addressable IDs for logical processors in this package) is
valid for the package.
29TM
Thermal Monitor.
The processor implements the thermal monitor automatic thermal control circuitry (TCC).
30ReservedReserved
31PBE
Pending Break Enable.
The processor supports the use of the FERR#/PBE# pin when the processor is in the
stop-clock state (STPCLK# is asserted) to signal the processor that an interrupt is pending and that the
processor should return to normal operation to handle the interrupt.
Table 3-11. More on Feature Information Returned in the EDX Register (Contd.)
Bit # Mnemonic Description
image/svg+xml
Table 3-12. Encoding of CPUID Leaf 2 Descriptors
ValueTypeDescription
00HGeneralNull descriptor, this byte contains no information
01HTLBInstruction TLB: 4 KByte pages, 4-way set associative, 32 entries
02HTLBInstruction TLB: 4 MByte pages, fully associative, 2 entries
03HTLBData TLB: 4 KByte pages, 4-way set associative, 64 entries
04HTLBData TLB: 4 MByte pages, 4-way set associative, 8 entries
05HTLBData TLB1: 4 MByte pages, 4-way set associative, 32 entries
06HCache1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size
08HCache1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size
09HCache1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size
0AHCache1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size
0BHTLBInstruction TLB: 4 MByte pages, 4-way set associative, 4 entries
0CHCache1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size
0DHCache1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size
0EHCache1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size
1DHCache2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size
21HCache2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size
22HCache3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector
23HCache3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector
24HCache2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size
25HCache3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector
29HCache3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector
2CHCache1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size
30HCache1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size
40HCacheNo 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache
41HCache2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size
42HCache2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size
43HCache2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size
44HCache2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size
45HCache2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size
46HCache3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size
47HCache3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size
48HCache2nd-level cache: 3MByte, 12-way set associative, 64 byte line size
49HCache3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model
06H);
2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size
4AHCache3rd-level cache: 6MByte, 12-way set associative, 64 byte line size
4BHCache3rd-level cache: 8MByte, 16-way set associative, 64 byte line size
4CHCache3rd-level cache: 12MByte, 12-way set associative, 64 byte line size
4DHCache3rd-level cache: 16MByte, 16-way set associative, 64 byte line size
4EHCache2nd-level cache: 6MByte, 24-way set associative, 64 byte line size
4FH TLBInstruction TLB: 4 KByte pages, 32 entries
image/svg+xml
50H TLB Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries
51HTLBInstruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries
52HTLBInstruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries
55HTLBInstruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries
56HTLBData TLB0: 4 MByte pages, 4-way set associative, 16 entries
57HTLBData TLB0: 4 KByte pages, 4-way associative, 16 entries
59HTLBData TLB0: 4 KByte pages, fully associative, 16 entries
5AHTLBData TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries
5BHTLBData TLB: 4 KByte and 4 MByte pages, 64 entries
5CHTLBData TLB: 4 KByte and 4 MByte pages,128 entries
5DHTLBData TLB: 4 KByte and 4 MByte pages,256 entries
60HCache1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size
61HTLBInstruction TLB: 4 KByte pages, fully associative, 48 entries
63HTLBData TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte
pages, 4-way set associative, 4 entries
64HTLBData TLB: 4 KByte pages, 4-way set associative, 512 entries
66HCache1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size
67HCache1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size
68HCache1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size
6AHCacheuTLB: 4 KByte pages, 8-way set associative, 64 entries
6BHCacheDTLB: 4 KByte pages, 8-way set associative, 256 entries
6CHCacheDTLB: 2M/4M pages, 8-way set associative, 128 entries
6DHCacheDTLB: 1 GByte pages, fully associative, 16 entries
70HCacheTrace cache: 12 K-
μ
op, 8-way set associative
71HCacheTrace cache: 16 K-
μ
op, 8-way set associative
72HCacheTrace cache: 32 K-
μ
op, 8-way set associative
76HTLBInstruction TLB: 2M/4M pages, fully associative, 8 entries
78HCache2nd-level cache: 1 MByte, 4-way set associative, 64byte line size
79HCache2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector
7AHCache2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector
7BHCache2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector
7CHCache2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector
7DHCache2nd-level cache: 2 MByte, 8-way set associative, 64byte line size
7FHCache2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size
80HCache2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size
82HCache2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size
83HCache2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size
84HCache2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size
85HCache2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size
86HCache2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size
87HCache2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size
Table 3-12. Encoding of CPUID Leaf 2 Descriptors (Contd.)
ValueTypeDescription