image/svg+xmlCOMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGSInstruction Operand EncodingDescriptionCompares the double-precision floating-point values in the low quadwords of operand 1 (first operand) and operand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unor-dered, greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unor-dered result is returned if either source operand is a NaN (QNaN or SNaN).Operand 1 is an XMM register; operand 2 can be an XMM register or a 64 bit memory location. The COMISD instruc-tion differs from the UCOMISD instruction in that it signals a SIMD floating-point invalid operation exception (#I) when a source operand is either a QNaN or SNaN. The UCOMISD instruction signals an invalid operation exception only if a source operand is an SNaN.The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.Software should ensure VCOMISD is encoded with VEX.L=0. Encoding VCOMISD with VEX.L=1 may encounter unpredictable behavior across different processor generations.OperationCOMISD (all versions)RESULT :=OrderedCompare(DEST[63:0] <> SRC[63:0]) {(* Set EFLAGS *) CASE (RESULT) OFUNORDERED: ZF,PF,CF := 111;GREATER_THAN: ZF,PF,CF := 000;LESS_THAN: ZF,PF,CF := 001;EQUAL: ZF,PF,CF := 100;ESAC;OF, AF, SF := 0; }Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescription66 0F 2F /rCOMISD xmm1, xmm2/m64AV/VSSE2Compare low double-precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly.VEX.LIG.66.0F.WIG 2F /rVCOMISD xmm1, xmm2/m64AV/VAVXCompare low double-precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly.EVEX.LLIG.66.0F.W1 2F /rVCOMISD xmm1, xmm2/m64{sae}BV/VAVX512FCompare low double-precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (w)ModRM:r/m (r)NANABTuple1 ScalarModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlIntel C/C++ Compiler Intrinsic EquivalentVCOMISD int _mm_comi_round_sd(__m128d a, __m128d b, int imm, int sae); VCOMISD int _mm_comieq_sd (__m128d a, __m128d b)VCOMISD int _mm_comilt_sd (__m128d a, __m128d b)VCOMISD int _mm_comile_sd (__m128d a, __m128d b)VCOMISD int _mm_comigt_sd (__m128d a, __m128d b)VCOMISD int _mm_comige_sd (__m128d a, __m128d b)VCOMISD int _mm_comineq_sd (__m128d a, __m128d b)SIMD Floating-Point ExceptionsInvalid (if SNaN or QNaN operands), Denormal.Other ExceptionsVEX-encoded instructions, see Table2-20, “Type 3 Class Exception Conditions”.EVEX-encoded instructions, see Table2-48, “Type E3NF Class Exception Conditions”.Additionally:#UDIf VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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