image/svg+xmlCMPPD—Compare Packed Double-Precision Floating-Point ValuesInstruction Operand EncodingDescriptionPerforms a SIMD compare of the packed double-precision floating-point values in the second source operand and the first source operand and returns the result of the comparison to the destination operand. The comparison pred-icate operand (immediate byte) specifies the type of comparison performed on each pair of packed values in the two source operands. EVEX encoded versions: The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand (first operand) is an opmask register. Comparison results are written to the destination operand under the writemask k2. Each comparison result is a single mask bit of 1 (comparison true) or 0 (comparison false).VEX.256 encoded version: The first source operand (second operand) is a YMM register. The second source operand (third operand) can be a YMM register or a 256-bit memory location. The destination operand (first operand) is a YMM register. Four comparisons are performed with results written to the destination operand. The result of each comparison is a quadword mask of all 1s (comparison true) or all 0s (comparison false).128-bit Legacy SSE version: The first source and destination operand (first operand) is an XMM register. The second source operand (second operand) can be an XMM register or 128-bit memory location. Bits (MAXVL-1:128) of the corresponding ZMM destination register remain unchanged. Two comparisons are performed with results written to bits 127:0 of the destination operand. The result of each comparison is a quadword mask of all 1s (comparison true) or all 0s (comparison false).Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescription66 0F C2 /r ibCMPPD xmm1, xmm2/m128, imm8AV/VSSE2Compare packed double-precision floating-point values in xmm2/m128 and xmm1 using bits 2:0 of imm8 as a comparison predicate.VEX.128.66.0F.WIG C2 /r ibVCMPPD xmm1, xmm2, xmm3/m128, imm8BV/VAVXCompare packed double-precision floating-point values in xmm3/m128 and xmm2 using bits 4:0 of imm8 as a comparison predicate.VEX.256.66.0F.WIG C2 /r ibVCMPPD ymm1, ymm2, ymm3/m256, imm8BV/VAVXCompare packed double-precision floating-point values in ymm3/m256 and ymm2 using bits 4:0 of imm8 as a comparison predicate.EVEX.128.66.0F.W1 C2 /r ibVCMPPD k1 {k2}, xmm2, xmm3/m128/m64bcst, imm8CV/VAVX512VLAVX512FCompare packed double-precision floating-point values in xmm3/m128/m64bcst and xmm2 using bits 4:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1.EVEX.256.66.0F.W1 C2 /r ibVCMPPD k1 {k2}, ymm2, ymm3/m256/m64bcst, imm8CV/VAVX512VLAVX512FCompare packed double-precision floating-point values in ymm3/m256/m64bcst and ymm2 using bits 4:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1.EVEX.512.66.0F.W1 C2 /r ibVCMPPD k1 {k2}, zmm2, zmm3/m512/m64bcst{sae}, imm8CV/VAVX512FCompare packed double-precision floating-point values in zmm3/m512/m64bcst and zmm2 using bits 4:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)Imm8NABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)Imm8CFullModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)Imm8

image/svg+xmlVEX.128 encoded version: The first source operand (second operand) is an XMM register. The second source operand (third operand) can be an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the destina-tion ZMM register are zeroed. Two comparisons are performed with results written to bits 127:0 of the destination operand.The comparison predicate operand is an 8-bit immediate:•For instructions encoded using the VEX or EVEX prefix, bits 4:0 define the type of comparison to be performed (see Table3-1). Bits 5 through 7 of the immediate are reserved. •For instruction encodings that do not use VEX prefix, bits 2:0 define the type of comparison to be made (see the first 8 rows of Table3-1). Bits 3 through 7 of the immediate are reserved. Table 3-1. Comparison Predicate for CMPPD and CMPPS Instructions Predicateimm8 ValueDescriptionResult: A Is 1st Operand, B Is 2nd OperandSignals #IA on QNANA >BA < BA = BUnordered1EQ_OQ (EQ)0HEqual (ordered, non-signaling)FalseFalseTrueFalseNoLT_OS (LT)1HLess-than (ordered, signaling)FalseTrueFalseFalseYesLE_OS (LE)2HLess-than-or-equal (ordered, signaling)FalseTrueTrueFalseYesUNORD_Q (UNORD)3HUnordered (non-signaling)FalseFalseFalseTrueNoNEQ_UQ (NEQ)4HNot-equal (unordered, non-signaling)TrueTrueFalseTrueNoNLT_US (NLT)5HNot-less-than (unordered, signaling)TrueFalseTrueTrueYesNLE_US (NLE)6HNot-less-than-or-equal (unordered, signaling)TrueFalseFalseTrueYesORD_Q (ORD)7HOrdered (non-signaling)TrueTrueTrueFalseNoEQ_UQ8HEqual (unordered, non-signaling)FalseFalseTrueTrueNoNGE_US (NGE)9HNot-greater-than-or-equal (unordered, signaling)FalseTrueFalseTrueYesNGT_US (NGT)AHNot-greater-than (unordered, signaling)FalseTrueTrueTrueYesFALSE_OQ(FALSE)BHFalse (ordered, non-signaling)FalseFalseFalseFalseNoNEQ_OQCHNot-equal (ordered, non-signaling)TrueTrueFalseFalseNoGE_OS (GE)DHGreater-than-or-equal (ordered, signaling)TrueFalseTrueFalseYesGT_OS (GT)EHGreater-than (ordered, signaling)TrueFalseFalseFalseYesTRUE_UQ(TRUE)FHTrue (unordered, non-signaling)TrueTrueTrueTrueNoEQ_OS10HEqual (ordered, signaling)FalseFalseTrueFalseYesLT_OQ11HLess-than (ordered, nonsignaling)FalseTrueFalseFalseNoLE_OQ12HLess-than-or-equal (ordered, nonsignaling)FalseTrueTrueFalseNoUNORD_S13HUnordered (signaling)FalseFalseFalseTrueYesNEQ_US14HNot-equal (unordered, signaling)TrueTrueFalseTrueYesNLT_UQ15HNot-less-than (unordered, nonsignaling)TrueFalseTrueTrueNoNLE_UQ16HNot-less-than-or-equal (unordered, nonsig-naling)TrueFalseFalseTrueNoORD_S17HOrdered (signaling)TrueTrueTrueFalseYesEQ_US18HEqual (unordered, signaling)FalseFalseTrueTrueYesNGE_UQ19HNot-greater-than-or-equal (unordered, non-signaling)FalseTrueFalseTrueNo

image/svg+xmlThe unordered relationship is true when at least one of the two source operands being compared is a NaN; the ordered relationship is true when neither source operand is a NaN. A subsequent computational instruction that uses the mask result in the destination operand as an input operand will not generate an exception, because a mask of all 0s corresponds to a floating-point value of +0.0 and a mask of all 1s corresponds to a QNaN. Note that processors with “CPUID.1H:ECX.AVX =0” do not implement the “greater-than”, “greater-than-or-equal”, “not-greater than”, and “not-greater-than-or-equal relations” predicates. These comparisons can be made either by using the inverse relationship (that is, use the “not-less-than-or-equal” to make a “greater-than” comparison) or by using software emulation. When using software emulation, the program must swap the operands (copying registers when necessary to protect the data that will now be in the destination), and then perform the compare using a different predicate. The predicate to be used for these emulations is listed in the first 8 rows of Table 3-7 (Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 2A) under the heading Emulation. Compilers and assemblers may implement the following two-operand pseudo-ops in addition to the three-operand CMPPD instruction, for processors with “CPUID.1H:ECX.AVX =0”. See Table3-2. Compiler should treat reserved Imm8 values as illegal syntax.:The greater-than relations that the processor does not implement require more than one instruction to emulate in software and therefore should not be implemented as pseudo-ops. (For these, the programmer should reverse the operands of the corresponding less than relations and use move instructions to ensure that the mask is moved to the correct destination register and that the source operand is left intact.)Processors with “CPUID.1H:ECX.AVX =1” implement the full complement of 32 predicates shown in Table3-3, soft-ware emulation is no longer needed. Compilers and assemblers may implement the following three-operand pseudo-ops in addition to the four-operand VCMPPD instruction. See Table3-3, where the notations of reg1 reg2, and reg3 represent either XMM registers or YMM registers. Compiler should treat reserved Imm8 values as illegal NGT_UQ1AHNot-greater-than (unordered, nonsignaling)FalseTrueTrueTrueNoFALSE_OS1BHFalse (ordered, signaling)FalseFalseFalseFalseYesNEQ_OS1CHNot-equal (ordered, signaling)TrueTrueFalseFalseYesGE_OQ1DHGreater-than-or-equal (ordered, nonsignal-ing)TrueFalseTrueFalseNoGT_OQ1EHGreater-than (ordered, nonsignaling)TrueFalseFalseFalseNoTRUE_US1FHTrue (unordered, signaling)TrueTrueTrueTrueYesNOTES:1. If either operand A or B is a NAN.Table 3-2. Pseudo-Op and CMPPD ImplementationPseudo-OpCMPPD ImplementationCMPEQPD xmm1, xmm2CMPPD xmm1, xmm2, 0CMPLTPD xmm1, xmm2CMPPD xmm1, xmm2, 1CMPLEPD xmm1, xmm2CMPPD xmm1, xmm2, 2CMPUNORDPD xmm1, xmm2CMPPD xmm1, xmm2, 3CMPNEQPD xmm1, xmm2CMPPD xmm1, xmm2, 4CMPNLTPD xmm1, xmm2CMPPD xmm1, xmm2, 5CMPNLEPD xmm1, xmm2CMPPD xmm1, xmm2, 6CMPORDPD xmm1, xmm2CMPPD xmm1, xmm2, 7Table 3-1. Comparison Predicate for CMPPD and CMPPS Instructions (Contd.)Predicateimm8 ValueDescriptionResult: A Is 1st Operand, B Is 2nd OperandSignals #IA on QNANA >BA < BA = BUnordered1

image/svg+xmlsyntax. Alternately, intrinsics can map the pseudo-ops to pre-defined constants to support a simpler intrinsic inter-face. Compilers and assemblers may implement three-operand pseudo-ops for EVEX encoded VCMPPD instructions in a similar fashion by extending the syntax listed in Table3-3.:Table 3-3. Pseudo-Op and VCMPPD ImplementationPseudo-OpCMPPD ImplementationVCMPEQPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 0VCMPLTPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 1VCMPLEPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 2VCMPUNORDPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 3VCMPNEQPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 4VCMPNLTPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 5VCMPNLEPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 6VCMPORDPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 7VCMPEQ_UQPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 8VCMPNGEPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 9VCMPNGTPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 0AHVCMPFALSEPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 0BHVCMPNEQ_OQPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 0CHVCMPGEPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 0DHVCMPGTPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 0EHVCMPTRUEPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 0FHVCMPEQ_OSPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 10HVCMPLT_OQPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 11HVCMPLE_OQPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 12HVCMPUNORD_SPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 13HVCMPNEQ_USPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 14HVCMPNLT_UQPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 15HVCMPNLE_UQPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 16HVCMPORD_SPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 17HVCMPEQ_USPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 18HVCMPNGE_UQPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 19HVCMPNGT_UQPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 1AHVCMPFALSE_OSPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 1BHVCMPNEQ_OSPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 1CHVCMPGE_OQPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 1DHVCMPGT_OQPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 1EHVCMPTRUE_USPD reg1, reg2, reg3VCMPPD reg1, reg2, reg3, 1FH

image/svg+xmlOperationCASE (COMPARISON PREDICATE) OF0: OP3 := EQ_OQ; OP5 := EQ_OQ;1: OP3 := LT_OS; OP5 := LT_OS;2: OP3 := LE_OS; OP5 := LE_OS;3: OP3 := UNORD_Q; OP5 := UNORD_Q;4: OP3 := NEQ_UQ; OP5 := NEQ_UQ;5: OP3 := NLT_US; OP5 := NLT_US;6: OP3 := NLE_US; OP5 := NLE_US;7: OP3 := ORD_Q; OP5 := ORD_Q;8: OP5 := EQ_UQ;9: OP5 := NGE_US;10: OP5 := NGT_US;11: OP5 := FALSE_OQ;12: OP5 := NEQ_OQ;13: OP5 := GE_OS;14: OP5 := GT_OS;15: OP5 := TRUE_UQ;16: OP5 := EQ_OS;17: OP5 := LT_OQ;18: OP5 := LE_OQ;19: OP5 := UNORD_S;20: OP5 := NEQ_US;21: OP5 := NLT_UQ;22: OP5 := NLE_UQ;23: OP5 := ORD_S;24: OP5 := EQ_US;25: OP5 := NGE_UQ;26: OP5 := NGT_UQ;27: OP5 := FALSE_OS;28: OP5 := NEQ_OS;29: OP5 := GE_OQ;30: OP5 := GT_OQ;31: OP5 := TRUE_US;DEFAULT: Reserved;ESAC;

image/svg+xmlVCMPPD (EVEX encoded versions)(KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 64IF k2[j] OR *no writemask*THEN IF (EVEX.b = 1) AND (SRC2 *is memory*)THENCMP := SRC1[i+63:i] OP5 SRC2[63:0]ELSE CMP := SRC1[i+63:i] OP5 SRC2[i+63:i]FI;IF CMP = TRUETHEN DEST[j] := 1;ELSE DEST[j] := 0; FI;ELSE DEST[j] := 0 ; zeroing-masking onlyFI;ENDFORDEST[MAX_KL-1:KL] := 0VCMPPD (VEX.256 encoded version)CMP0 := SRC1[63:0] OP5 SRC2[63:0];CMP1 := SRC1[127:64] OP5 SRC2[127:64];CMP2 := SRC1[191:128] OP5 SRC2[191:128];CMP3 := SRC1[255:192] OP5 SRC2[255:192];IF CMP0 = TRUETHEN DEST[63:0] := FFFFFFFFFFFFFFFFH;ELSE DEST[63:0] := 0000000000000000H; FI;IF CMP1 = TRUETHEN DEST[127:64] := FFFFFFFFFFFFFFFFH;ELSE DEST[127:64] := 0000000000000000H; FI;IF CMP2 = TRUETHEN DEST[191:128] := FFFFFFFFFFFFFFFFH;ELSE DEST[191:128] := 0000000000000000H; FI;IF CMP3 = TRUETHEN DEST[255:192] := FFFFFFFFFFFFFFFFH;ELSE DEST[255:192] := 0000000000000000H; FI;DEST[MAXVL-1:256] := 0VCMPPD (VEX.128 encoded version)CMP0 := SRC1[63:0] OP5 SRC2[63:0];CMP1 := SRC1[127:64] OP5 SRC2[127:64];IF CMP0 = TRUETHEN DEST[63:0] := FFFFFFFFFFFFFFFFH;ELSE DEST[63:0] := 0000000000000000H; FI;IF CMP1 = TRUETHEN DEST[127:64] := FFFFFFFFFFFFFFFFH;ELSE DEST[127:64] := 0000000000000000H; FI;DEST[MAXVL-1:128] := 0

image/svg+xmlCMPPD (128-bit Legacy SSE version)CMP0 := SRC1[63:0] OP3 SRC2[63:0];CMP1 := SRC1[127:64] OP3 SRC2[127:64];IF CMP0 = TRUETHEN DEST[63:0] := FFFFFFFFFFFFFFFFH;ELSE DEST[63:0] := 0000000000000000H; FI;IF CMP1 = TRUETHEN DEST[127:64] := FFFFFFFFFFFFFFFFH;ELSE DEST[127:64] := 0000000000000000H; FI;DEST[MAXVL-1:128] (Unmodified)Intel C/C++ Compiler Intrinsic EquivalentVCMPPD __mmask8 _mm512_cmp_pd_mask( __m512d a, __m512d b, int imm);VCMPPD __mmask8 _mm512_cmp_round_pd_mask( __m512d a, __m512d b, int imm, int sae);VCMPPD __mmask8 _mm512_mask_cmp_pd_mask( __mmask8 k1, __m512d a, __m512d b, int imm);VCMPPD __mmask8 _mm512_mask_cmp_round_pd_mask( __mmask8 k1, __m512d a, __m512d b, int imm, int sae);VCMPPD __mmask8 _mm256_cmp_pd_mask( __m256d a, __m256d b, int imm);VCMPPD __mmask8 _mm256_mask_cmp_pd_mask( __mmask8 k1, __m256d a, __m256d b, int imm);VCMPPD __mmask8 _mm_cmp_pd_mask( __m128d a, __m128d b, int imm);VCMPPD __mmask8 _mm_mask_cmp_pd_mask( __mmask8 k1, __m128d a, __m128d b, int imm);VCMPPD __m256 _mm256_cmp_pd(__m256d a, __m256d b, int imm)(V)CMPPD __m128 _mm_cmp_pd(__m128d a, __m128d b, int imm)SIMD Floating-Point ExceptionsInvalid if SNaN operand and invalid if QNaN and predicate as listed in Table3-1.DenormalOther ExceptionsVEX-encoded instructions, see Table2-19, “Type 2 Class Exception Conditions”.EVEX-encoded instructions, see Table2-46, “Type E2 Class Exception Conditions”.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.