image/svg+xmlCMOVcc—Conditional MoveOpcodeInstructionOp/ En64-Bit ModeCompat/Leg ModeDescription0F 47 /rCMOVA r16, r/m16RMValidValidMove if above (CF=0 and ZF=0).0F 47 /rCMOVA r32, r/m32RMValidValidMove if above (CF=0 and ZF=0).REX.W + 0F 47 /rCMOVA r64, r/m64RMValidN.E.Move if above (CF=0 and ZF=0).0F 43 /rCMOVAE r16, r/m16RMValidValidMove if above or equal (CF=0).0F 43 /rCMOVAE r32, r/m32RMValidValidMove if above or equal (CF=0).REX.W + 0F 43 /rCMOVAE r64, r/m64RMValidN.E.Move if above or equal (CF=0).0F 42 /rCMOVB r16, r/m16RMValidValidMove if below (CF=1).0F 42 /rCMOVB r32, r/m32RMValidValidMove if below (CF=1).REX.W + 0F 42 /rCMOVB r64, r/m64RMValidN.E.Move if below (CF=1).0F 46 /rCMOVBE r16, r/m16RMValidValidMove if below or equal (CF=1 or ZF=1).0F 46 /rCMOVBE r32, r/m32RMValidValidMove if below or equal (CF=1 or ZF=1).REX.W + 0F 46 /rCMOVBE r64, r/m64RMValidN.E.Move if below or equal (CF=1 or ZF=1).0F 42 /rCMOVC r16, r/m16RMValidValidMove if carry (CF=1).0F 42 /rCMOVC r32, r/m32RMValidValidMove if carry (CF=1).REX.W + 0F 42 /rCMOVC r64, r/m64RMValidN.E.Move if carry (CF=1).0F 44 /rCMOVE r16, r/m16RMValidValidMove if equal (ZF=1).0F 44 /rCMOVE r32, r/m32RMValidValidMove if equal (ZF=1).REX.W + 0F 44 /rCMOVE r64, r/m64RMValidN.E.Move if equal (ZF=1).0F 4F /rCMOVG r16, r/m16RMValidValidMove if greater (ZF=0 and SF=OF).0F 4F /rCMOVG r32, r/m32RMValidValidMove if greater (ZF=0 and SF=OF).REX.W + 0F 4F /rCMOVG r64, r/m64RMV/N.E.NAMove if greater (ZF=0 and SF=OF).0F 4D /rCMOVGE r16, r/m16RMValidValidMove if greater or equal (SF=OF).0F 4D /rCMOVGE r32, r/m32RMValidValidMove if greater or equal (SF=OF).REX.W + 0F 4D /rCMOVGE r64, r/m64RMValidN.E.Move if greater or equal (SF=OF).0F 4C /rCMOVL r16, r/m16RMValidValidMove if less (SF≠ OF).0F 4C /rCMOVL r32, r/m32RMValidValidMove if less (SF≠ OF).REX.W + 0F 4C /rCMOVL r64, r/m64RMValidN.E.Move if less (SF≠ OF).0F 4E /rCMOVLE r16, r/m16RMValidValidMove if less or equal (ZF=1 or SF≠ OF).0F 4E /rCMOVLE r32, r/m32RMValidValidMove if less or equal (ZF=1 or SF≠ OF).REX.W + 0F 4E /rCMOVLE r64, r/m64RMValidN.E.Move if less or equal (ZF=1 or SF≠ OF).0F 46 /rCMOVNA r16, r/m16RMValidValidMove if not above (CF=1 or ZF=1).0F 46 /rCMOVNA r32, r/m32RMValidValidMove if not above (CF=1 or ZF=1).REX.W + 0F 46 /rCMOVNA r64, r/m64RMValidN.E.Move if not above (CF=1 or ZF=1).0F 42 /rCMOVNAE r16, r/m16RMValidValidMove if not above or equal (CF=1).0F 42 /rCMOVNAE r32, r/m32RMValidValidMove if not above or equal (CF=1).REX.W + 0F 42 /rCMOVNAE r64, r/m64RMValidN.E.Move if not above or equal (CF=1).0F 43 /rCMOVNB r16, r/m16RMValidValidMove if not below (CF=0).0F 43 /rCMOVNB r32, r/m32RMValidValidMove if not below (CF=0).REX.W + 0F 43 /rCMOVNB r64, r/m64RMValidN.E.Move if not below (CF=0).0F 47 /rCMOVNBE r16, r/m16RMValidValidMove if not below or equal (CF=0 and ZF=0).

image/svg+xmlOpcodeInstructionOp/ En64-Bit ModeCompat/Leg ModeDescription0F 47 /rCMOVNBE r32, r/m32RMValidValidMove if not below or equal (CF=0 and ZF=0).REX.W + 0F 47 /rCMOVNBE r64, r/m64RMValidN.E.Move if not below or equal (CF=0 and ZF=0).0F 43 /rCMOVNC r16, r/m16RMValidValidMove if not carry (CF=0).0F 43 /rCMOVNC r32, r/m32RMValidValidMove if not carry (CF=0).REX.W + 0F 43 /rCMOVNC r64, r/m64RMValidN.E.Move if not carry (CF=0).0F 45 /rCMOVNE r16, r/m16RMValidValidMove if not equal (ZF=0).0F 45 /rCMOVNE r32, r/m32RMValidValidMove if not equal (ZF=0).REX.W + 0F 45 /rCMOVNE r64, r/m64RMValidN.E.Move if not equal (ZF=0).0F 4E /rCMOVNG r16, r/m16RMValidValidMove if not greater (ZF=1 or SF≠ OF).0F 4E /rCMOVNG r32, r/m32RMValidValidMove if not greater (ZF=1 or SF≠ OF).REX.W + 0F 4E /rCMOVNG r64, r/m64RMValidN.E.Move if not greater (ZF=1 or SF≠ OF).0F 4C /rCMOVNGE r16, r/m16RMValidValidMove if not greater or equal (SF≠ OF).0F 4C /rCMOVNGE r32, r/m32RMValidValidMove if not greater or equal (SF≠ OF).REX.W + 0F 4C /rCMOVNGE r64, r/m64RMValidN.E.Move if not greater or equal (SF≠ OF).0F 4D /rCMOVNL r16, r/m16RMValidValidMove if not less (SF=OF).0F 4D /rCMOVNL r32, r/m32RMValidValidMove if not less (SF=OF).REX.W + 0F 4D /rCMOVNL r64, r/m64RMValidN.E.Move if not less (SF=OF).0F 4F /rCMOVNLE r16, r/m16RMValidValidMove if not less or equal (ZF=0 and SF=OF).0F 4F /rCMOVNLE r32, r/m32RMValidValidMove if not less or equal (ZF=0 and SF=OF).REX.W + 0F 4F /rCMOVNLE r64, r/m64RMValidN.E.Move if not less or equal (ZF=0 and SF=OF).0F 41 /rCMOVNO r16, r/m16RMValidValidMove if not overflow (OF=0).0F 41 /rCMOVNO r32, r/m32RMValidValidMove if not overflow (OF=0).REX.W + 0F 41 /rCMOVNO r64, r/m64RMValidN.E.Move if not overflow (OF=0).0F 4B /rCMOVNP r16, r/m16RMValidValidMove if not parity (PF=0).0F 4B /rCMOVNP r32, r/m32RMValidValidMove if not parity (PF=0).REX.W + 0F 4B /rCMOVNP r64, r/m64RMValidN.E.Move if not parity (PF=0).0F 49 /rCMOVNS r16, r/m16RMValidValidMove if not sign (SF=0).0F 49 /rCMOVNS r32, r/m32RMValidValidMove if not sign (SF=0).REX.W + 0F 49 /rCMOVNS r64, r/m64RMValidN.E.Move if not sign (SF=0).0F 45 /rCMOVNZ r16, r/m16RMValidValidMove if not zero (ZF=0).0F 45 /rCMOVNZ r32, r/m32RMValidValidMove if not zero (ZF=0).REX.W + 0F 45 /rCMOVNZ r64, r/m64RMValidN.E.Move if not zero (ZF=0).0F 40 /rCMOVO r16, r/m16RMValidValidMove if overflow (OF=1).0F 40 /rCMOVO r32, r/m32RMValidValidMove if overflow (OF=1).REX.W + 0F 40 /rCMOVO r64, r/m64RMValidN.E.Move if overflow (OF=1).0F 4A /rCMOVP r16, r/m16RMValidValidMove if parity (PF=1).0F 4A /rCMOVP r32, r/m32RMValidValidMove if parity (PF=1).REX.W + 0F 4A /rCMOVP r64, r/m64RMValidN.E.Move if parity (PF=1).0F 4A /rCMOVPE r16, r/m16RMValidValidMove if parity even (PF=1).0F 4A /rCMOVPE r32, r/m32RMValidValidMove if parity even (PF=1).REX.W + 0F 4A /rCMOVPE r64, r/m64RMValidN.E.Move if parity even (PF=1).

image/svg+xmlInstruction Operand EncodingDescriptionEach of the CMOVcc instructions performs a move operation if the status flags in the EFLAGS register (CF, OF, PF, SF, and ZF) are in a specified state (or condition). A condition code (cc) is associated with each instruction to indi-cate the condition being tested for. If the condition is not satisfied, a move is not performed and execution continues with the instruction following the CMOVcc instruction.Specifically, CMOVcc loads data from its source operand into a temporary register unconditionally (regardless of the condition code and the status flags in the EFLAGS register). If the condition code associated with the instruction (cc) is satisfied, the data in the temporary register is then copied into the instruction's destination operand.These instructions can move 16-bit, 32-bit or 64-bit values from memory to a general-purpose register or from one general-purpose register to another. Conditional moves of 8-bit register operands are not supported.The condition for each CMOVcc mnemonic is given in the description column of the above table. The terms “less” and “greater” are used for comparisons of signed integers and the terms “above” and “below” are used for unsigned integers.Because a particular state of the status flags can sometimes be interpreted in two ways, two mnemonics are defined for some opcodes. For example, the CMOVA (conditional move if above) instruction and the CMOVNBE (conditional move if not below or equal) instruction are alternate mnemonics for the opcode 0F 47H. The CMOVcc instructions were introduced in P6 family processors; however, these instructions may not be supported by all IA-32 processors. Software can determine if the CMOVcc instructions are supported by checking the processor’s feature information with the CPUID instruction (see “CPUID—CPU Identification” in this chapter).In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to addi-tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.Operationtemp := SRCIF condition TRUETHEN DEST := temp;ELSE IF (OperandSize = 32 and IA-32e mode active)THEN DEST[63:32] := 0;FI;OpcodeInstructionOp/ En64-Bit ModeCompat/Leg ModeDescription0F 4B /rCMOVPO r16, r/m16RMValidValidMove if parity odd (PF=0).0F 4B /rCMOVPO r32, r/m32RMValidValidMove if parity odd (PF=0).REX.W + 0F 4B /rCMOVPO r64, r/m64RMValidN.E.Move if parity odd (PF=0).0F 48 /rCMOVS r16, r/m16RMValidValidMove if sign (SF=1).0F 48 /rCMOVS r32, r/m32RMValidValidMove if sign (SF=1).REX.W + 0F 48 /rCMOVS r64, r/m64RMValidN.E.Move if sign (SF=1).0F 44 /rCMOVZ r16, r/m16RMValidValidMove if zero (ZF=1).0F 44 /rCMOVZ r32, r/m32RMValidValidMove if zero (ZF=1).REX.W + 0F 44 /rCMOVZ r64, r/m64RMValidN.E.Move if zero (ZF=1).Op/EnOperand 1Operand 2Operand 3Operand 4RMModRM:reg (r, w)ModRM:r/m (r)NANA

image/svg+xmlFlags AffectedNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SS segment limit.#UD If the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made.#UD If the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.