image/svg+xmlBNDMOV—Move BoundsInstruction Operand EncodingDescriptionBNDMOV moves a pair of lower and upper bound values from the source operand (the second operand) to the destination (the first operand). Each operation is 128-bit move. The exceptions are same as the MOV instruction. The memory format for loading/store bounds in 64-bit mode is shown in Figure3-5.This instruction does not change flags.OperationBNDMOV register to registerDEST.LB := SRC.LB; DEST.UB := SRC.UB; Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription66 0F 1A /rBNDMOV bnd1, bnd2/m64RMNE/VMPXMove lower and upper bound from bnd2/m64 to bound register bnd1.66 0F 1A /rBNDMOV bnd1, bnd2/m128RMV/NEMPXMove lower and upper bound from bnd2/m128 to bound register bnd1.66 0F 1B /rBNDMOV bnd1/m64, bnd2MRNE/VMPXMove lower and upper bound from bnd2 to bnd1/m64.66 0F 1B /rBNDMOV bnd1/m128, bnd2MRV/NEMPXMove lower and upper bound from bnd2 to bound register bnd1/m128.Op/EnOperand 1Operand 2Operand 3RMModRM:reg (w)ModRM:r/m (r)NAMRModRM:r/m (w)ModRM:reg (r)NAFigure 3-5. Memory Layout of BNDMOV to/from MemoryUpper Bound (UB)Lower Bound (LB)8016Byte offsetBNDMOV to memory in 64-bit modeUpper Bound (UB)Lower Bound (LB)8016Byte offsetBNDMOV to memory in 32-bit mode4

image/svg+xmlBNDMOV from memoryIF 64-bit mode THENDEST.LB := LOAD_QWORD(SRC); DEST.UB := LOAD_QWORD(SRC+8); ELSEDEST.LB := LOAD_DWORD_ZERO_EXT(SRC); DEST.UB := LOAD_DWORD_ZERO_EXT(SRC+4); FI;BNDMOV to memoryIF 64-bit mode THENDEST[63:0] := SRC.LB; DEST[127:64] := SRC.UB; ELSEDEST[31:0] := SRC.LB; DEST[63:32] := SRC.UB; FI;Intel C/C++ Compiler Intrinsic EquivalentBNDMOV void * _bnd_copy_ptr_bounds(const void *q, const void *r)Flags AffectedNoneProtected Mode Exceptions#UDIf the LOCK prefix is used but the destination is not a memory operand.If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.If 67H prefix is not used and CS.D=0.If 67H prefix is used and CS.D=1.#SS(0)If the memory operand effective address is outside the SS segment limit.#GP(0)If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the destination operand points to a non-writable segmentIf the DS, ES, FS, or GS segment register contains a NULL segment selector.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.#PF(fault code)If a page fault occurs.Real-Address Mode Exceptions#UDIf the LOCK prefix is used but the destination is not a memory operand.If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.If 16-bit addressing is used.#GP(0)If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SSIf the memory operand effective address is outside the SS segment limit.

image/svg+xmlVirtual-8086 Mode Exceptions#UDIf the LOCK prefix is used but the destination is not a memory operand.If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.If 16-bit addressing is used.#GP(0)If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SS(0)If the memory operand effective address is outside the SS segment limit.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.#PF(fault code)If a page fault occurs.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#UDIf the LOCK prefix is used but the destination is not a memory operand.If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.#SS(0)If the memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.#PF(fault code)If a page fault occurs.

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