image/svg+xmlBNDCU/BNDCN—Check Upper BoundInstruction Operand EncodingDescriptionCompare the address in the second operand with the upper bound in bnd. The second operand can be either a register or a memory operand. If the address is higher than the upper bound in bnd.UB, it will set BNDSTATUS to 01H and signal a #BR exception.BNDCU perform 1’s complement operation on the upper bound of bnd first before proceeding with address compar-ison. BNDCN perform address comparison directly using the upper bound in bnd that is already reverted out of 1’s complement form. This instruction does not cause any memory access, and does not read or write any flags. Effective address computation of m32/64 has identical behavior to LEAOperationBNDCU BND, regIF reg > NOT(BND.UB) ThenBNDSTATUS := 01H; #BR; FI;BNDCU BND, memTEMP := LEA(mem); IF TEMP > NOT(BND.UB) ThenBNDSTATUS := 01H; #BR; FI;BNDCN BND, regIF reg > BND.UB ThenBNDSTATUS := 01H; #BR; FI;Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionF2 0F 1A /rBNDCU bnd, r/m32RMNE/VMPXGenerate a #BR if the address in r/m32 is higher than the upper bound in bnd.UB (bnb.UB in 1's complement form).F2 0F 1A /rBNDCU bnd, r/m64RMV/NEMPXGenerate a #BR if the address in r/m64 is higher than the upper bound in bnd.UB (bnb.UB in 1's complement form).F2 0F 1B /rBNDCN bnd, r/m32RMNE/VMPXGenerate a #BR if the address in r/m32 is higher than the upper bound in bnd.UB (bnb.UB not in 1's complement form).F2 0F 1B /rBNDCN bnd, r/m64RMV/NEMPXGenerate a #BR if the address in r/m64 is higher than the upper bound in bnd.UB (bnb.UB not in 1's complement form).Op/EnOperand 1Operand 2Operand 3RMModRM:reg (w)ModRM:r/m (r)NA

image/svg+xmlBNDCN BND, memTEMP := LEA(mem); IF TEMP > BND.UB ThenBNDSTATUS := 01H; #BR; FI;Intel C/C++ Compiler Intrinsic EquivalentBNDCU .void _bnd_chk_ptr_ubounds(const void *q)Flags AffectedNoneProtected Mode Exceptions#BRIf upper bound check fails.#UDIf the LOCK prefix is used.If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.If 67H prefix is not used and CS.D=0.If 67H prefix is used and CS.D=1.Real-Address Mode Exceptions#BRIf upper bound check fails.#UDIf the LOCK prefix is used.If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.If 16-bit addressing is used.Virtual-8086 Mode Exceptions#BRIf upper bound check fails.#UDIf the LOCK prefix is used.If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.If 16-bit addressing is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#UDIf ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.Same exceptions as in protected mode.

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