image/svg+xmlBNDCL—Check Lower BoundInstruction Operand EncodingDescriptionCompare the address in the second operand with the lower bound in bnd. The second operand can be either a register or memory operand. If the address is lower than the lower bound in bnd.LB, it will set BNDSTATUS to 01H and signal a #BR exception.This instruction does not cause any memory access, and does not read or write any flags. OperationBNDCL BND, regIF reg < BND.LB ThenBNDSTATUS := 01H; #BR; FI;BNDCL BND, memTEMP := LEA(mem); IF TEMP < BND.LB ThenBNDSTATUS := 01H; #BR; FI;Intel C/C++ Compiler Intrinsic EquivalentBNDCL void _bnd_chk_ptr_lbounds(const void *q)Flags AffectedNoneProtected Mode Exceptions#BRIf lower bound check fails.#UDIf the LOCK prefix is used.If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.If 67H prefix is not used and CS.D=0.If 67H prefix is used and CS.D=1.Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionF3 0F 1A /rBNDCL bnd, r/m32RMNE/VMPXGenerate a #BR if the address in r/m32 is lower than the lower bound in bnd.LB.F3 0F 1A /rBNDCL bnd, r/m64RMV/NEMPXGenerate a #BR if the address in r/m64 is lower than the lower bound in bnd.LB.Op/EnOperand 1Operand 2Operand 3RMModRM:reg (w)ModRM:r/m (r)NA

image/svg+xmlReal-Address Mode Exceptions#BRIf lower bound check fails.#UDIf the LOCK prefix is used.If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.If 16-bit addressing is used.Virtual-8086 Mode Exceptions#BRIf lower bound check fails.#UDIf the LOCK prefix is used.If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.If 16-bit addressing is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#UDIf ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.Same exceptions as in protected mode.

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