image/svg+xml BLSR — Reset Lowest Set Bit Instruction Operand Encoding Description Copies all bits from the source operand to the destination operand and resets (=0) the bit position in the destina- tion operand that corresponds to the lowest set bit of the source operand. If the source operand is zero BLSR sets CF. This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD. Operation temp := (SRC-1) bitwiseAND ( SRC ); SF := temp[OperandSize -1]; ZF := (temp = 0); IF SRC = 0 CF := 1; ELSE CF := 0; FI DEST := temp; Flags Affected ZF and SF flags are updated based on the result. CF is set if the source is zero. OF flag is cleared. AF and PF flags are undefined. Intel C/C++ Compiler Intrinsic Equivalent BLSR:unsigned __int32 _blsr_u32(unsigned __int32 src); BLSR:unsigned __int64 _blsr_u64(unsigned __int64 src); SIMD Floating-Point Exceptions None Other Exceptions See Table2-29, “Type 13 Class Exception Conditions”. Opcode/InstructionOp/ En 64/32 -bit Mode CPUID Feature Flag Description VEX.LZ.0F38.W0 F3 /1 BLSR r32, r/m32 VMV/VBMI1Reset lowest set bit of r/m32, keep all other bits of r/m32 and write result to r32. VEX.LZ.0F38.W1 F3 /1 BLSR r64, r/m64 VMV/N.E.BMI1Reset lowest set bit of r/m64, keep all other bits of r/m64 and write result to r64. Op/EnOperand 1Operand 2Operand 3Operand 4 VMVEX.vvvv (w)ModRM:r/m (r)NANA This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .